# Computer "bits" and memory. **URL:** \ **Category:** Factual Questions\ **Created:** [September 1, 2012, 6:49am UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344 "2012-09-01T06:49:45Z")\ **Posts on this page:** 9\ **Page:** 2
**Author:** ![Francis\_Vaughan](https://sea3.discourse-cdn.com/straightdope/user_avatar/boards.straightdope.com/francis_vaughan/32/3093_2.png) [@Francis\_Vaughan](https://boards.straightdope.com/u/Francis_Vaughan)\ **Post date:** [September 1, 2012, 4:13pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/21 "2012-09-01T16:13:22Z")
> [@](#): > > they took the opportunity to add a lot more internal “general purpose registers”. Yup, this is the single biggest win. It accounts for up to a doubling in performance, all by itself. (Depending as usual on exactly what it is you are doing. Easily a 50% improvement on many codes.) Where it loses is that addresses have doubled in width, and that means your pointers are twice as big, and so cache doesn’t hold as much program data - which can be important and so you lose speed here. This is enough of a problem that there is now a X32 ABI under development - 64 bit data, with the 16 64 bit registers, but addresses are restricted to 32 bits, and the compilers will only store the low 32 bits of the addresses. So you get all the advantages of the x86-64 ISA, but keep the advantages of the tighter memory of the 32 bit addresses. The reality being that the vast majority of codes don’t, and never will, need bigger than a 32 bit address space. ---
**Author:** ![notsoheavyd3](https://avatars.discourse-cdn.com/v4/letter/n/85e7bf/32.png) [@notsoheavyd3](https://boards.straightdope.com/u/notsoheavyd3)\ **Post date:** [September 1, 2012, 4:19pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/22 "2012-09-01T16:19:17Z")
> [@jz78817](#): > > _sigh_ data bus width does not determine what “bitness” the CPU is. The “bitness” of the CPU is generally held to be the width of the main registers and the width of the ALU(s.) The 8088 was a 16-bit CPU because its GPRs were 16 bits wide, and the ALU had a data word size of 16 bits. That Intel lopped off half of the bus pins to make it cheaper does not make it an 8-bit CPU in any way, shape, or form. Besides, even though it was a 16-bit CPU it had (kludgy) 20-bit addressing to support up to 1 MB of memory. Actually that’s the exact definition we got in my computer hardware course when I was getting my CS degree. So for example we did assembly on a 68000 emulator and that chip was described as 16-bit because it had a 16-bit databus. (Although apparently the ALU is 16-bit but they do 32bit arithmetic by doing the lower section of 16-bits and then the upper.) Of course this was like 20 years ago so I might not be totally clear. ---
**Author:** ![TriPolar](https://sea3.discourse-cdn.com/straightdope/user_avatar/boards.straightdope.com/tripolar/32/3008_2.png) [@TriPolar](https://boards.straightdope.com/u/TriPolar)\ **Post date:** [September 1, 2012, 4:30pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/23 "2012-09-01T16:30:24Z")
> [@jz78817](#): > > _sigh_ data bus width does not determine what “bitness” the CPU is. The “bitness” of the CPU is generally held to be the width of the main registers and the width of the ALU(s.) The 8088 was a 16-bit CPU because its GPRs were 16 bits wide, and the ALU had a data word size of 16 bits. That Intel lopped off half of the bus pins to make it cheaper does not make it an 8-bit CPU in any way, shape, or form. Besides, even though it was a 16-bit CPU it had (kludgy) 20-bit addressing to support up to 1 MB of memory. There is no specific definition of what bit width indicates. It means different things in different contexts, and there is no privileged context. > [@](#): > > You are still confusing bus width and memory addressing. stop it. The width of the data bus has nothing to do with the amount of addressable memory. The width of the data bus in part defines bandwidth. The “Bitness” of the processor’s ALUs and AGUs defines how much memory it can address. Again, context. When discussing bus width and addressing, you are referring to the largest address which can be placed on the bus at one time. That’s all. There is a difference between logical and physical addressing at many different levels, and your individual perspective doesn’t make any of them the proper one. So stopping making those baseless assumptions. ---
**Author:** ![Derleth](https://avatars.discourse-cdn.com/v4/letter/d/b9e5f3/32.png) [@Derleth](https://boards.straightdope.com/u/Derleth)\ **Post date:** [September 1, 2012, 6:05pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/24 "2012-09-01T18:05:14Z")
[Here’s what John R. Mashey has to say about ‘bittedness’ in computer architecture](http://homepages.cwi.nl/~robertl/mash/128vs32): ```auto historically, when people called a CPU "N-bits", the "N" normally meant the width the regular integer registers, NOT the width of floating-point or other special registers NOT the width of external busses NOT the width of other special datapaths NOT the size of instructions Occasionally, as in the Intel i860 (where a 32-bit CPU with a 64-bit bus was labeled a 64-bit CPU), or in games/graphics devices labeled as 128-bit devices (that normally incorporate 32- or 64-bit CPUs using the historical definitions), marketing gets the upper hand, at which point some people declare that the terminology is confused. As far as I can tell, people who actually design CPUs rarely are confused about "bittedness", and marketing diversions have been relatively rare. ``` Given that [Mashey helped design MIPS and is one of the founders of the SPEC benchmarking group, I’m inclined to believe him.](http://en.wikipedia.org/wiki/John_Mashey) ---
**Author:** ![Derleth](https://avatars.discourse-cdn.com/v4/letter/d/b9e5f3/32.png) [@Derleth](https://boards.straightdope.com/u/Derleth)\ **Post date:** [September 1, 2012, 6:12pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/25 "2012-09-01T18:12:03Z")
> [@jz78817](#): > > actually, x86 processors since the Pentium Pro have supported 36-bit addressing through PAE and could theoretically use up to 64 GB of memory. True for the OS, but (as I understand it) applications could only ever use 32-bit pointers, so they were limited to the 4 GB address space. ---
**Author:** ![Learjeff](https://avatars.discourse-cdn.com/v4/letter/l/94ad74/32.png) [@Learjeff](https://boards.straightdope.com/u/Learjeff)\ **Post date:** [September 1, 2012, 7:03pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/26 "2012-09-01T19:03:16Z")
I agree with TriPolar that the term, when unqualified, is ambiguous. But I’ll agree with Derleth that it’s most commonly the ALU bit width, and the width of the general-purpose registers, that’s the one most commonly meant when unqualified. (Chips where the ALU width doesn’t match the GP register width are oddballs we needn’t be concerned with here. I can’ t think of any off the top of my head, but I’m sure there’s an exception to every generalization about CPU architecture!) However, a CPU is many things and has many things, all of which can have different widths, so to say “CPU bit width of xxx” is to be ambiguous. Derleth is also correct that the big difference (address-wise) for 64-bit architectures is for a single program to be able to directly access over 4GB of data. Even the OS can’t do that, but it can set up a number of programs to run concurrently that together access more than 4GB. ---
**Author:** ![septimus](https://sea3.discourse-cdn.com/straightdope/user_avatar/boards.straightdope.com/septimus/32/410_2.png) [@septimus](https://boards.straightdope.com/u/septimus)\ **Post date:** [September 1, 2012, 8:40pm UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/27 "2012-09-01T20:40:25Z")
Bit-width can be ambiguous. For example, the IBM 370/145 had almost all its registers and data-paths 32-bits, but the bus from main memory was 64 bits, with half the data discarded in _almost_ every (but not every!) case. Its ALU was only 16 bits but it did 32-bit arithmetic by simply cycling the ALU twice in one instruction cycle. (The ALU handled only 8 bits per instruction cycle when doing Boolean ops – the data was duplicated and the halves of ALU output compared for error checking. :eek:) ---
**Author:** ![Simple\_Linctus](https://avatars.discourse-cdn.com/v4/letter/s/9f8e36/32.png) [@Simple\_Linctus](https://boards.straightdope.com/u/Simple_Linctus)\ **Post date:** [September 2, 2012, 1:21am UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/28 "2012-09-02T01:21:55Z")
> [@septimus](#): > > a smart Googler might then be able to discover my secret identity. 🆒 Totally did that, although I will provide no evidence of it whatsoever. Therefore you have nothing to lose by spilling all the beans 😉 ---
**Author:** ![Michael63129](https://avatars.discourse-cdn.com/v4/letter/m/3da27b/32.png) [@Michael63129](https://boards.straightdope.com/u/Michael63129)\ **Post date:** [September 2, 2012, 2:10am UTC](https://boards.straightdope.com/t/computer-bits-and-memory/633344/29 "2012-09-02T02:10:14Z")
Some GPUs use data bus widths [as large as 512 bits](http://www.brightsideofnews.com/news/2009/5/5/gt300-to-feature-512-bit-interface---nvidia-set-to-continue-with-complicated-controllers.aspx), although they are still only 32 bits internally (note that the article ends with erroneously calling it a “512 bit GPU”). Also, the number of actual address lines isn’t necessarily what you might expect; a CPU with a 64 bit data bus accesses 8 bytes at once, which can be seen as the lowest 3 address bits, so to address 4 GB, you only need 29 physical address lines, the same is true of a RAM module with a data bus multiple bytes wide (64 bits for DDR, with modules often combined so that the total bus width is larger). [Previous page](https://boards.straightdope.com/t/computer-bits-and-memory/633344.md?page=1)