# Computer Speed (July 4, 2003) **URL:** \ **Category:** Cecil's Columns/Staff Reports\ **Created:** [July 4, 2003, 7:53am UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205 "2003-07-04T07:53:37Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![Major\_Kong](https://avatars.discourse-cdn.com/v4/letter/m/b9bd4f/32.png) [@Major\_Kong](https://boards.straightdope.com/u/Major_Kong)\ **Post date:** [July 4, 2003, 7:53am UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/1 "2003-07-04T07:53:37Z")
[http://www.straightdope.com/columns/030704.html](http://www.straightdope.com/columns/030704.html) > [@](#): > > But Gordon Moore, cofounder of Intel and originator in 1965 of Moore’s Law (current formulation: computer power per square inch of microchip doubles every 18 months), says **we won’t haul up against the laws of physics, or at least the limits of wafer technology, until 2017.** Can someone explain what the limits of wafer technology are? ---
**Author:** ![Major\_Kong](https://avatars.discourse-cdn.com/v4/letter/m/b9bd4f/32.png) [@Major\_Kong](https://boards.straightdope.com/u/Major_Kong)\ **Post date:** [July 4, 2003, 7:54am UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/2 "2003-07-04T07:54:45Z")
Oh yeah, bolding mine. ---
**Author:** ![Colophon](https://avatars.discourse-cdn.com/v4/letter/c/f05b48/32.png) [@Colophon](https://boards.straightdope.com/u/Colophon)\ **Post date:** [July 4, 2003, 5:53pm UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/3 "2003-07-04T17:53:13Z")
Basically it means the limit of how many circuits you can fit on a given area of silicon chip, before the insulating “gaps” between electric pathways get so thin that they no longer effectively insulate. Her’s a brief explanation from [this page](http://www.zurich.ibm.com/news/01/invest.html): > [@](#): > > Size and performance of individual transistors on microelectronic chips depend to a large extent on a thin layer between the transistor gate and the semiconducting silicon. This layer must have dielectric properties, i.e. no current flows through the material but a charge is built up by applying an electrical field at the gate. The charge causes a conducting channel to be formed in the silicon below the layer, thus switching on the transistor. For the past three decades, dielectric layers have been made of silicon dioxide as a cornerstone of silicon-based integrated circuits. > > The dielectric properties desired in transistors depend on the geometry of the structure, i.e. both area and thickness of the layer must be reduced proportionally with shrinking devices. Miniaturization now approaches a limit where the silicon-dioxide layer becomes too thin and risks losing its insulating properties, leading to a leakage current. By the way, [this _Nature_ article](http://www.nature.com/nsu/990624/990624-1.html) says the limit will be reached sooner, in about 2012. FYI, currently the gate oxide layer in commercial chips is about 25 atoms thick. Anything less than four or five atoms will likely be “so leaky as to be useless”. ---
**Author:** ![Paul.Streeter](https://avatars.discourse-cdn.com/v4/letter/p/48db29/32.png) [@Paul.Streeter](https://boards.straightdope.com/u/Paul.Streeter)\ **Post date:** [July 4, 2003, 6:36pm UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/4 "2003-07-04T18:36:46Z")
I once saw a picture of Microsoft’s terraserver, on which they have all the satellite pictures they could get, Us, Russian, et al. It was a set of Compaq Alpha servers. I also asked to see my employer’s IBM MVS computer. The mainframe was a cabinet similar in size to an Alpha server. The mainframes have become physically smaller but more powerful while the pc based ones have become a bit larger and a lot more powerful. Cubic foot for cubic foot, as far as I can tell, the IBM mainframe can still kick a pc’s motherboard all over the place. LANs and WANs provide immense flexibility of course. One reason the mainframe won’t go away is that it is a kickass database server, connecting to the LAN despite the fact that the use different binary schemes to represent data. ---
**Author:** ![GRobLewis](https://avatars.discourse-cdn.com/v4/letter/g/b5e925/32.png) [@GRobLewis](https://boards.straightdope.com/u/GRobLewis)\ **Post date:** [July 4, 2003, 7:22pm UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/5 "2003-07-04T19:22:46Z")
Just for the record, supercomputer performance claims are as ripe for abuse as anything else. The most common ploy is to hook together hundreds or thousands of commodity microprocessors and claim you now have a “teraflop” machine (these are known in the trade as “massively parallel” systems). In theory, yes. In practice, almost never. Not even close. It’s unusual to get even 10% of the theoretical peak performance out of such a machine on “real world” problems, and on many important problems it won’t do a whole lot better than a desktop PC. And massively parallel machines are a nightmare to program. If you want extreme performance on real-world problems, you have to get a real supercomputer, like a Cray. Their new machines are awesome. ---
**Author:** ![Tim\_T-Bonham.net](https://avatars.discourse-cdn.com/v4/letter/t/46a35a/32.png) [@Tim\_T-Bonham.net](https://boards.straightdope.com/u/Tim_T-Bonham.net)\ **Post date:** [July 4, 2003, 8:24pm UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/6 "2003-07-04T20:24:35Z")
Much of the reason for the “inefficiency” of massively parallel systems is due to the lack of good software for them. Our computers for the past 50 years have been pipeline rather than parallel processors, and so we have 50 years of software tuned for that type of system. Also, our problems seem to be mainly an algorothimic or ‘pipeline’ type of problem – where you must solve step 1 before you can start on step 2, etc. (Or maybe we’ve just taught ourselves that those kind of problems are the only ones that are effectively ‘computable’. Or maybe several centuries of using the ‘scientific method’ means current scientists mostly come up with pipeline rather than parallel solutions to problems.) A lot of the work in using massively parallel systems involves producing software that can automate the conversion of ‘pipeline’ problems into ones that can be solved in parallel. We haven’t been able to do so very efficiently, so far. But they’ve only been working at this for a couple of decades, vs. 3 times as long on regular computers. I expect massively parallel systems will become more effective in the future, as programmers fine tune the software for them, and as scientists come up with ‘parallel’ algorithims that run effectively on such machines. ---
**Author:** ![GRobLewis](https://avatars.discourse-cdn.com/v4/letter/g/b5e925/32.png) [@GRobLewis](https://boards.straightdope.com/u/GRobLewis)\ **Post date:** [July 4, 2003, 9:44pm UTC](https://boards.straightdope.com/t/computer-speed-july-4-2003/186205/7 "2003-07-04T21:44:17Z")
No doubt software for MP systems will improve eventually; however the last 20 years of intensive work have produced little fruit and much teeth-gnashing. Even if that problem were solved, however, certain classes of important problems simply don’t adapt well to MP architecture–you wind up spending most of your time exchanging messages between the processors and little time actually computing. Examples are sparse matrix problems, and those involving finite element analysis where the mesh is dynamically resized. For jobs like this, there’s no substitute for a very large, flat, shared memory, which MP systems don’t offer.