Thanks JohnClay, I never use ctrl-alt-del because I have a freeware taskmanager but I will check it out!
Well, in a sense this is letting multiple processes run without the overhead of context switching. True parallelism is here in the UltraSparcIV, which has two Sparc CPUs on one chip. Niagara, which is on its way, has I think 8, each of which can handle two threads. Intel has just decided to go this way.
However, in a sense all processors run more than one instruction at a time through pipelining. Since each CISC instruction takes more than one clock, it goes through several stages of a pipeline, followed by others - so three or four may be executing at once. Also, there are often multiple copies of units like multipliers which take a long time to complete, so more than one multiply can be happening at time. Other instructions may be waiting for a cache miss.
But if you are in an idle loop, not much of anything is happening at the moment.
With modern chips, electromigration is a real concern for the designers. This can cause the interconnects to “wear out” and fail. If the chip is properly designed, it will be replaced long before this becomes a concern, due to the equipment being old or obsolete.