I meant: Homer, I want the links that you alluded.
Urban Ranger: Nope, I was discussing the P4. Intel made a design decision to make the P4 EXTREMELY inefficient on a per-clock basis, in order to get a much higher clock speed number to impress consumers. Hence why a 2Ghz P4 (with the integer unit actually running at 4Ghz) is beaten by a 1667Mhz Athlon XP (XP 2000+). The Itanium isn’t even designed to run x86 applications, so it runs them at about the speed of a Pentium 100. This would be OK if it actually ran decently with applications that were expressly designed for it, but that’s the subject of another thread
capacitor: Answer, the P4 is purchased because Intel has a brand name. IMHO, the P4 is not an example of “Innovation doesn’t work because applications need to be remade,” but rather an example of how NOT to build a CPU. Intel designed a CPU that was technically inferior to everything else on the market, then tried to work around it. Even so, a 2.53Ghz P4 isn’t exactly slow. If you build a system around it, CPU dependent apps WILL go faster, even if you don’t recompile them to access the P4’s new features.
Check out nVidia’s nForce chipset… dual 64-bit memory controllers that can function together at 128-bit bandwidth. The new new chipset, the 620 IIRC, will do 333MHz DDR. I have the previous 266 generation, and it smokes. If the chipset scales well and the RAM is high quality, that will be scary.
*Originally posted by Capacitor * **I have a feeling that the faster machines are there to cover up the slow speeds of certain programming languages. If Java had the speed of, say, Pascal, then even Bill Gates will have to bow to the feet of Scott McNealy. **[/QUOTE}
Java is improving, but C++ still rules the roost in the x86 world… If Gates had a real stranglehold, he’d want to keep CPUs slow so his natively coded Windows apps would have an edge over other approaches, no?
<—wanders off muttering something about hitting the wrong bloody button…
The_Raven: The nForce’s dual-channel memory controller is designed exclusively to feed the onboard Geforce2 MX. The system bus will never see more bandwidth than a standard single-channel controller. We’ll have to wait for AMD to release CPUs based on a 166Mhz DDR FSB, or overclock, to improve this situation.
If someone were to develop a dual-channel PC2100 DDR chipset for the new 133Mhz QDR FSB P4s, this would actually pose a serious threat to AMD. It would provide the P4 with equal bandwidth to dual-channel PC1066 RDRAM, AND at a much lower latency and price. I’m not holding my breath for a decent P4 solution to come out, however. I’m waiting on the new AMD Thoroughbreds:)