# VHDL Help please.

**URL:** <https://boards.straightdope.com/t/vhdl-help-please/175599>\
**Category:** Factual Questions\
**Created:** [May 16, 2003, 3:14am UTC](https://boards.straightdope.com/t/vhdl-help-please/175599 "2003-05-16T03:14:27Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![Cubsfan](https://avatars.discourse-cdn.com/v4/letter/c/f4b2a3/32.png) [@Cubsfan](https://boards.straightdope.com/u/Cubsfan)\
**Post date:** [May 16, 2003, 3:14am UTC](https://boards.straightdope.com/t/vhdl-help-please/175599/1 "2003-05-16T03:14:27Z")

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I am writing this VHDL to make a 7 segment display driver for school. I am having problems with the selected signal assignment at the bottom of this code. It keeps giving me an error that says that “choice value length (4) must match selector value expression length”. I have been looking at this for an hour now and can’t figure out what I Am doing wrong.

The only part of the code that is not compiling is that last piece. All of the IF/Then stuff works fine. I included all of it in here just incase someone wanted to see it  
\*\*  
library ieee;  
use ieee.std\_logic\_1164.all;

ENTITY ssd IS  
PORT(  
b0, b1, b2, b3 : in bit;  
a,c,e,f : out bit  
);   
END ssd;

ARCHITECTURE operation OF ssd IS  
begin  
process (b0, b1, b2, b3)  
BEGIN

```
	IF((b3 AND b2) = '1') THEN
		c&lt;=(NOT b1 AND b0);
	ELSIF (NOT b3 AND NOT b2 AND NOT b0 AND b1) = '1' THEN
		c&lt;= '0';
	ELSE
		c&lt;= '1';
		
	END	IF;
end process;

process (b0, b1, b2, b3)
BEGIN
	
	IF ((not b3 and b2)= '1') THEN
		e&lt;= (b1 and not b0);
	elsif ((not b1 and b0)= '1') THEN
		e&lt;= (b3 and b2);
	elsif ((b0 and b1 and not b3 and not b2)= '1') THEN
		e&lt;= '0';
	else e&lt;= '1';
end if;
end process;

process (b0, b1, b2, b3)
BEGIN

	IF ((not b3 and not b2)= '1') then
		f&lt;= (not b1 and not b0);
	elsif ((not b3 and b2 and b1 and b0)= '1') then
		f&lt;= '0';
	elsif ((b3 and b2 and not b1 and b0)= '1') then
		f&lt;= '0';
	else f&lt;= '1';
end if;
end process;

*WITH b0 & b1 & b2 & b3 SELECT
	a&lt;= '0' when "0001",
		'0' when "0100",
		'0' when "1101",
		'0' when "1011",
		'1' when others;

```

- 

END operation;\*\*

The part in italics is the part that I am having problems with. I think I may be referencing my inputs wrong.

Anyone have any idea where this simple error is at?

Thanks.

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<div class="post-metadata">

**Author:** ![Cubsfan](https://avatars.discourse-cdn.com/v4/letter/c/f4b2a3/32.png) [@Cubsfan](https://boards.straightdope.com/u/Cubsfan)\
**Post date:** [May 16, 2003, 11:52am UTC](https://boards.straightdope.com/t/vhdl-help-please/175599/2 "2003-05-16T11:52:58Z")

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Bumping for the day shift.

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**Author:** ![Mort\_Furd](https://avatars.discourse-cdn.com/v4/letter/m/8e8cbc/32.png) [@Mort\_Furd](https://boards.straightdope.com/u/Mort_Furd)\
**Post date:** [May 16, 2003, 4:09pm UTC](https://boards.straightdope.com/t/vhdl-help-please/175599/3 "2003-05-16T16:09:56Z")

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I’m not familiar with VHDL, but programming in general. I’ve looked up some syntax on the WITH key word, and I have an idea.

The error message and what I’ve read suggests that the values on each side of the WHEN must be of the same length - which also implies that your ‘a’ must also be of the same length.

Just a suggestion.

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<div class="post-metadata">

**Author:** ![gazpacho](https://avatars.discourse-cdn.com/v4/letter/g/6f9a4e/32.png) [@gazpacho](https://boards.straightdope.com/u/gazpacho)\
**Post date:** [May 16, 2003, 5:12pm UTC](https://boards.straightdope.com/t/vhdl-help-please/175599/4 "2003-05-16T17:12:07Z")

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Try making a bus for b0 b1 b2 and b3. I never use bit but instead use STD\_LOGIC and STD\_LOGIC\_VECTOR. Why are you using bit and not STD\_LOGIC?

b\_bus \<= b0 & b1 & b2 & b3;

WITH b\_bus SELECT  
a\<= ‘0’ when “0001”,  
‘0’ when “0100”,  
‘0’ when “1101”,  
‘0’ when “1011”,  
‘1’ when others;