Note also that processor makers are now developing notebook-specific processors. If somebody could chime in on what the Pentium 4-M (Centrino?) processor does to specifically use less power/generate less heat, I would be interested in learning.
I’m guessing it’s a combination of the smaller transistors plus not adding as many more transisters as the desktop model, plus running them slower (but still more than fast enough for the average user).
-lv
One thing I don’t believe has been mentioned so far - they’re also working to lower the voltrage at which processors and other devices run. This means less of the voltage swing referred to earlier, and on balance less total power consumed. A while back almost everything digital ran at (nominally) 5.0 volts. 3.3V was popular for a while and then 2.5. I believ many parts used in pc’s, like memories, are now running at 1.5V.
what david simmons said, also realise there are parasitic capacitances that must be charged and discharged on every switching and this means current and heat.
transistors might be getting smaller and less power hungry but at the same time we’re getting more and more of them, and they switch faster and faster. each transistor doesnt eat much but take 50 million of them switching many billion times per second …
after all, processor clock speed is NOT the speed at which transistors switch. transistors switch several times faster still. a clock tick corresponds to some sort of suboperation (one link of pipeline) that will require a lot more than a transistor switching once.
think of it, UNLESS A TRANSISTOR IS SPENDING A GOOD PART OF ITS TIME ACTUALLY SWITCHING (as opposed to being on or off) THEN YOU COULD PROBABLY CLOCK IT FASTER AND GET MORE PERFORMANCE. thus you should not think of switching as something that takes a short time relative to how often it happens. rather transistor should only spend enough time in a state between switches for the next transistor inline to reliably register its state.
Yes, I was referring overlapping conduction in a totem-pole arrangement. Under normal operating conditions, this is less of a problem with CMOS gates than it was with TTL. But if that was the only major factor in active power consumption, you could just use ECL and avoid the cross-over issues.
And earlier someone else had mentioned zero rise/fall times. While this would reduce overlapping bias currents, there are practical limitations. Faster slew rates mean you have to driver larger drive currents at higher frequencies, which increases problems such as crosstalk, and undershoot/overshoot. Crosstalk becomes more of a problem as IC features become smaller and closer together. I’m not actually sure how much of a problem undershoot is in the IC domain. I’m more familiar with the tranmission effects on PCB assemblies. On an IC, the distances are usually too short for tranmission line effects, though I would still think you would have to worry about overdriving a circuit and creating undershoot. The problem with large undershoot is that you can forward bias a PN junction that wasn’t supposed to be forward biased, and then you’ll get to see some serious power consumption, along with a brief glow and some smoke.
re lowering voltages, reducing the voltage swings in digital signals is really helpful from a signal integrity POV. Plus, it’s also easier to switch at higher speeds if your voltage swings are smaller. On the practical side, you still need to maintain adequate noise margins for your logic levels.
FYI, the Pentium 4-M and Centrinio are separate processors designs. The Pentium 4-M is basically slightly modified Pentium 4, designed to step-down its clock speed when you don’t need it; it is still pretty bad when it comes to power consumption.
The Centrinio is, IIRC, based off of the Pentium3 core, which is actually more efficient (as in it does more processing per clock cycle than the Pentium 4. A 1.4Ghz P3 will beat a 1.6Ghz P4 in most applications.) than the Pentium 4, allowing it to run at lower clock speeds and still get acceptable performance. The Centrinioes also can reduce their clockspeed when it is not need.
I thought the on-chip cache used static RAM, which doesn’t need to be refreshed…?
The Intel Centrino (Pentium-M) is not based on the Pentium III. It is a redesigned Pentium 4, optimized for low power usage and performance. This Anandtech article goes into detail about the design of the Centrino. Most notable is the shorter pipeline, which means more performance per clock.
In the future, Asynchronous Processors will be able to deliver much greater performance with much reduced power usage.
It’s the body heat from all the miniature hamsters, friction of their wheels, and decaying tiny cedar chips that have become urine soaked.
>>computers usually have a heatsink to draw the heat away, and a fan mounted on top.
fyi: Not all computers have fans.
[Nyaah, nyaah] I’m typing this on a silent computer. [/Nyaah, nyaah]
Umm, reading the article you posted does suggest that many features from the Pentium III were used in the Pentium-M. And it seems a LOT more like a P3 than the Pentium 4. For example, they have the same execution unit layout.
The Pentium-M was designed, as noted in the article, by a group that had worked extensively on the Pentium III. The Pentium III is a CPU that was well-designed for its day, and was markedly efficient. Any processor that is similarly designed to be efficient is going to share some traits with the P3, notable a relatively short pipeline and thus low clockspeeds. In truth, the Pentium-M is a new CPU design, if it’s based on anything it’s the P4, though it was strongly influenced by the design methodologies of its creators.