Thinking about silicon wafers here. Back in the dark ages when I had physics classes at university, it seemed to be an article of faith that you can’t accurately image anything smaller than the wavelength of the light you are using to observe it.
Which would seem to imply that you can’t accurately project a smaller image either.
As far as I can tell, the current tech uses 13 nm extreme ultraviolet for etching, but the chip feature sizes I have heard are quite a bit smaller (3 or even 2 nm have been mentioned).
I got the impression somebody someplace created interference patterns to create some simple sort of photolithography. This would have created repeating structures, though their geometry wouldn’t have been arbitrary, it would have had to follow some shape. Could this be it?
I’m embarrassed to say I don’t actually know or remember whether interference patterns can be smaller than the wavelengths used to create them – though I should. Optics 201 was a long time ago.
There are many different techniques at play. One of them is double-patterning (as well as triple patterning, etc.).
Imagine that you tune your photoresist and exposure time so that only those parts that are near the peak of the sine wave are cured. This leaves you lines that are much narrower than your wavelength, but the minimum spacing between lines is still the wavelength.
However, you can then shift your mask by a fraction of a wavelength, and create lines that are at a different offset. Do it enough times and you can fill in the large gaps, leaving lines at a much closer spacing than the wavelength.
Another trick is called immersion lithography. The idea is simple: the photoresist is put under a film of water. Since the speed of light is slower with a higher index of refraction, the effective wavelength goes down. That makes a typical 193 nm laser operate as if it were 134 nm.
Wouldn’t this something also have to be transparent to work? As well as non-corrosive, non-reactive with the photo-resistive ink, etc.
That might limit the liquids that can be used.
I agree that it seems like an obvious idea, but I haven’t heard of anything except ultrapure water being used. There are definitely a number of significant constraints. Cost and compatibility with other processing steps will be a big one. I did find this patent:
Still other immersion fluids that have been considered for 15 nm immersion lithography are KRYTOX™ and perfluoropolyether (PFPE).
Searching for these, I can find some mentions of them in the literature, but no examples of them being used.
I think that ultimately, the materials problem just gets too hard/expensive, and you end up better off going with EUV (extreme ultraviolet, using a 13.5 nm laser). There are numerous challenges there as well, but it’s a “reset” in terms of tech maturity, and further improvements are relatively easier.
Right, I’m sure there are a lot of constraints. And I’m not enough of an inorganic chemist to make any actual suggestions. There are probably quite a lot of bright and well informed scientists looking into this, since it is, after all, a very obvious idea.
To be clear, the CMOS technology nodes started out as straightforward measures of something on the wafer, usually the gate length. Using standard transistor designs, gate length could be used to predict the number of transistors one could stuff into a square mm of chip area (Moore’s Law!). Somewhere below a micron, they started to represent “effective” dimensions. Once they got below about 22 nm, the transistors became vertical (FinFets) so they simply didn’t represent a physical dimension at all. They also had to abandon Deep UV along the way in favor of EUV.
The node numbers aren’t made up or imaginary, though. They more or less represent the dimension required in the straightforward calculation to stuff the number of transistors they can actually stuff into a square mm of chip area.
However, they aren’t marketing hype. The customers for these technology nodes are spending increasing amounts to design these chips ( ~$100M at 5nm, with mask sets costing $10-15M alone) so they are not going to be persuaded by a new number alone. Their ROI is predicted on the cost of a wafer ($17K at 7 nm) , how many chips they can get off a wafer, and the volume of chip sales that will cover the design costs.
Here are a couple of interesting reads that will give you some insight into the extreme technoogy applications that are taking place and the associated costs:
The machines to make the latest chip are insanely high-tech:
Weighing more than 10 metric tons, it consists of 450,000 individual parts. As the system’s light source, this laser generates plasma with a temperature of 220,000°C, which is 30 to 40 times hotter than temperatures on the surface of the sun. The giant laser is aimed at a stream of tin droplets inside the lithography system, where it strikes and flattens 50,000 of these tiny droplets every second. Actually, the giant laser takes two shots at each of these tin droplets, with the second hit transforming the flattened droplet into plasma that emits the precious EUV light.
That machine is like the Manhattan Project multiplied by the Apollo program.
It was surprising to me to learn about their Rube Goldberg laser system, as opposed to using a free-electron laser, but I don’t know what the natural limits are. I did find this from 2010: 13.5-nm FREE-ELECTRON LASER FOR EUV LITHOGRAPHY
They propose a 40x20 m facility, which is rather large. It seems like there’s a practical lower limit to the size, which might be too big. The FEL achieves a whopping 0.1% efficiency and 5 kW beam power, compared to the hot tin approach with 0.02% efficiency and 200 W beam power.