The Basics of Microchip Design

How do you go from a logic model or the like to an actual mask you can use to create working microchips?

I realize this must be a rather complex topic, given the amount of effort a company needs to put into any modern microchip project. But I’m astounded that humans are able to productize such a profoundly complex piece of machinery, to stamp things out that are more densely complex than anything humans ever made in the pre-microchip era. All I’m looking for is some idea of how the process works.

I have plenty of programming experience and a basic understanding of transistors and how electrons work. I understand quantum mechanics well enough to follow Scientific American-type articles on advances in that field. I even have a VHDL `compiler’ with example code, but I’ll be damned if I can make sense of some of it.

I have a BSc in E.E. I know the process of photolithography and semiconductor doping in great detail, as well as some basic principles on CMOS logic design, but mask manufacturing was not in the curriculum. :confused:

Hard to know where to start. To try to kick things off:

A modern microprocessor might look incredibly complex, but it’s important to note from the outset that you don’t start completely from scratch each time.

You have a series of building blocks, starting with transistors, which can be regarded as switches. The transistors can be configured to form larger building blocks: an array of them can be set up as a small unit of memory, e.g. a register, or as a logic processor, e.g. and AND gate. You can take those larger building blocks and make still larger ones, e.g. string registers together to form a cache memory, or gates to form an ALU.

It’s already known how to make these building blocks, and how to put them together to form a microprocessor.

A “new” microprcessor design will try to improve some aspect of existing designs. The transistors might be smaller. Or the architecture somehow different, e.g. to use 128 bit registers instead of 64 or 32, or to have 6 ALUs operating in parallel instead of 3.

Think of it in software terms. If you want to write a new accounting program, you don’t have write the whole thing in hex machine code, work out a good way to sort an array of numbers, work out how to write characters onto the screen, etc. All that stuff’s already been done.

Does that help you to refine the question at all?

Dog80: If you know anything about microchip design, add your two cents. My first sentence was an example, something to give people a vague idea of what I am asking about.

Desmostylus: I know that the chip is divided into reusable parts, and that certain problems have been solved in the general case. And, as a software guy, I’m all about solving a problem once and then reusing that solution as often as I can.

Perhaps this will refine my query:

I’ve seen VHDL code. I’ve seen enlarged views of microchips. I have no farking idea how you get from one to the other. That is, compiling a logic design into a physical object with multiple and complex interconnections between all of the components (the ALU, the register file, the cache, etc.) simply seems like magic to me.

I understand how you can build an adder from transistors, and how you can use transistors to create RAM and/or registers. But how do you put it all together?

(If I’m completely up the wrong tree here (for example, if no self-respecting chipmaker would ever touch VHDL), set me straight. I know I’m out of my league here.)

I have no idea how it’s done, but I can guess…

(1) Chip machine drawing software reads next line/segment of chip spec

(2) Chip machine drawing software determines exactly which components are needed for that segment; i.e., how many transistors and what type, how many resistors and their resistance values, etc.

(3) Chip machine software pulls out enlarged photo of each component of the requisite spec from its files and makes a new photographic print containing all of them.

(4) New print added to final print queue.

(5) Return to step (1) until finished.

Ok, some chip manufactruring basics:

I’m going to say a few things about the wafer only, I don’t have time right now

Chips are made on a silicon wafer which looks like this:
http://www.addisonengineering.com/GRAPHICS/silicon-wafer2.gif
This is one of the biggest ones, probably 9 or 12 inches, there are smaller ones as well

The wafer is an extremely pure piece of Si crystal with as little lattice defects as possible. The side shown in that picture is the “wrong” side of the wafer. The chips are printed on the other side, which is highly polished (using a combination of chemical and mechanical processes) and with a thin layer of SiO2 (essentialy glass) grown on it. This layer is extremely important during the photolithography process, because it protects the glass covered areas of the Si from getting doped.

This is a finished wafer http://lupus.gsfc.nasa.gov/brochure/mark_iv_chip.gif
The chips are the little squares (called dies). These will be cut and tested. Those dies that pass the test will be “packaged”.
The completed chips will be tested again, and those that pass are good to be sold.

Note that the die is tiny compared to the completed packaged chip. In this picture, the die is the tiny green square in the middle. http://www.tezzaron.com/about/PhotoAlbum/Products/images/Chip.jpg
Each of the tiny wires that fan out of the die finishes to a pin on the other side of the chip.

die=singular, dice=plural :smack:

Dog80: This is probably my fault, but I understand photolithography and the physical process of transferring an image of a chip to silicon. I even understand doping and how the layers of different chemicals make a chip work electrically.

It’s a fascinating subject that deserves its own thread, just not this one.

What I’m interested in is how we go from the parts we know how to build (the basic components, such as the adders and the registers and such) and a new chip idea (the ISA, the pipeline depth, and so on) to an actual image we can mask onto the die.

It might help if you add a few more layers of abstraction. Start out with the idea, say a simple 8-bit microprocessor, break that down into blocks such as register bank, ALU, instruction decoder, memory interface, address bus, data bus, timing generator, control ROM. Take each block and create a logic diagram showing gates, flip-flops and simple registers. At this point, you could build a prototype from simple logic chips and wire-wrap boards. We have a list of the components and how they are wired together. Now take each simple logic chip and break it down into resistor, capacitors, diodes and transistors. These are all standard designs for a given logic family, so we have a library of hand-designed mini-masks for each standard logic device. Like designing a printed circuit board, we need to place each logic device on the mask and route the connections between the logic devices. In the old days, this was all done by hand, with sheets of colored mylar and an x-acto knife. The chip layout is then decomposed into multiple masks, depending on how many layers the chip has and the process being used. Each color in the layout corresponds to a layer or mask.

Here’s a possibly stupid question:

Why do we always use circular wafers to make a bunch of rectangular chips? You’d think a rectangle would be a more optimal shape. The circle causes lots of wasted silicon.

The wafers are slices of a cylindrical silicon crystal that is grown in a furnace. The crystal looks like a large salami before it is sliced into wafers.

Also, it’s hard enough to manufacture good chips at the edge of a round wafer. It would be practically impossible to make good devices at the corners of a square wafer.

It is magic in a sense. The same magic that runs human civilization: the gradual accumulation of prior solutions and approaches into something no individual or manageable group could accomplish from scratch in a reasonable time.

You already understand about the smal scale functional building blocks. These are well within the ability of a single person to design. In fact, there are many sets of solutions – “logic families” like TTL (Transistor-Transistor Logic), RTL (Resistor-Transistor Logic) and on a different level, CMOS, are basically sets of building blocks with a common approach, yielding a compatible set of building blocks, taking into account factors like substrate and doping, trace timing, signal thresholds, and timing (on this level, all digital circuits are analog) I don’t do this for a living, so I may list some of the properties in the wrong category below (and tests may occur in different stages depending on the specific tools you use), but I hope it’ll help you understand the process – to the extent I do, anyway.

Once you have a basic overall design, there are many tools that largely automate the process. First, you set up “design rules” to specify parameters related to the target design and IC technology design voltage thresholds, timing, propagation, and spacing. A program called a DRC or Design Rule Checker constantly checks your design as you lay in the circuit, and alerts you to issues interactively.

Similarly, there are “electrical rules” checked by an Electrical Rule Checker (ERC), which take into account the materials (e.g. substrate, doping, electrical properties at a given feature size like insulation and antenna properties of traces, etc.) and manufacturing constraints and properties (e.g. diffusion, breakdown, lithography limitations and imperfection tolerance, etc.) for a given technology and manufacturing facility. Actually, you usually choose a compromise: local personnel experience, conditions, suppliers and even climate can affect production – though this is controlled as tightly as possible.

Different facilities with the same equipment in the same company may have quite different yields. Factories tweak techniques and physical production parameters to improve yields over the course of a production yield, so generally a cutting edge chip aims for electrical rules that are expected to be achievable at low yield at present; Improvements over existing capabilities (within the theoretical capabilities of the underlying technology) are not just expected during the production run, they are almost demanded! For most chips, the Electrical Rules and Design Rules can be looked up in an in-house book, but for cutting edge chips, it’s a mix of art, marketing, and finger-crossing

Once the design is finally entered (with any changes required by the rule checkers) it is written in EDIF format and run through run through a circuit simulator (e.g. SPICE or Verilog) for extended and detailed checking. Some of the tests create virtual oscilloscope traces of expected waveform at various points in the circuit, so the design can be tweaked. Other tests are extended automated runs looking for glitches.

Routing is also an important task. Crossover, leakage, antenna properties and timing issues (e.g. often signals from different circuit block on different parts of a chip must arrive at their destination with tight synchrony) are crucial on the scale of modern CPUS. To do this, the tested circuit resulting formthe circuit simulations is converted to a network description, and tested in that paradigm. this si called Network Consistency Checking (NCC) or “Layout vs. Schematic” (LVS) testing. After it passes this stage, it is “disambiguated” (a process which I think I understood once, but can recall at the moment. “Disambiguated” comes from the root word “Ambiguity”) to create a workable design to be compacted for efficent packing.

Your VHDL compiler creates a link list between basic low-level building blocks, which can be compacted (usually by alternating vertical and horizontal compaction passes, aided by a little skilled human experience and intuition) and then run through yet another level of simulated testing (like RSIM) and eventually into a Silicon Compiler. Modern silicon compilers don’t just create a basic mask, but can also perform tests like “Logical Effort” which help them determine optimal feature size for a given target speed, layout and timing, etc., etc.

Doing a search for some of the key terms above, I found several manuals that seem to provide fairly clear but detailed descriptions fo the process and options for specific tool-sets. I think they should answer any question that you might have. The one for the Electric™ VLSI Design System looked pretty instructive to me, and would at least suggest the search terms for more specific topic reseach, If you don’t like that one, “VHDL compiler” seems to be a good single search term to find the manuals for other packages. Pretty much every IC design package either has a VHDL compiler (if they don’t, they’d have to explain what they use in its place)

I hope that helps, and isn’t too confusing. Dammit, Jim, I’m a doctor, not a semiconductor manufacturing engineer!

I don’t know how or why, but my link to the manual for the Electric™ VLSI Design System vanished somehow. (There, that’s better) I can’t vouch for the program, but the manual seemed clear but succinct to me. Try starting with Chapter 9 (“Tools”) before you go back to read the whole thing. Good stuff!

In the early days of microchip design, companies employed highly skilled “draftsmen” who would take the circuit diagrams chip designers gave them and translate them into mask diagrams. Chip deseigners would specify the relavent electrical parameters for the gates (drive current, etc) and the draftsmen would adjust the mask layout parameters accordingly. It was a real art, and these folks were paid very well.

Most of that function is now automated, but the process is essentially the same. If I need a “strong” transistor (one that can drive a number of gates quickly) then I must lay out the mask desgn so that the gate length is sufficiently large. Metal interconnect is very tricky since parasitic inductances from the many layers can interfere with how the circuit functions, and lends itself more to automation since it’s virtually impossible for a human to keep that level of compexity in his head.

But the basic premise is the same-- a given electrical parameter translates into a given physical dimension(s) on the chip.

Is this what you’re getting at?

Oops. Replace “length” with “width” in that post, above. IIRC, the term “width” is generally used to signifcy how big a given gate is.

mks57: Is breadboarding like that still done? Because I can understand that really well. For some reason, it didn’t occur to me to think in those terms.

KP: Thanks for all of your detail! I will check out your link, and I think I’m on the right path.

John Mace: Yes, that’s what I’m getting at: Taking the ideas about the chip, the components we have to work with, and all of the rules we know about designing these things, and turning it into a working product.

I understand how the design is transferred to the silicon and how the transistors work in terms of the properties of the materials and how electrons flow, and I understand how you can design a component like an adder out of the physical logic gates you have to work with. (In fact, I’ve drawn out my own simple adder by chaining gates together on paper. It was something like a four-bit adder, I think, but it showed the basic idea. Of course, that has more to do with Boolean algebra than electrical engineering.) I am beginning to understand, and this is where this thread comes in, how you can connect the components in all the myriad ways you would need to create a reasonably complex microchip.

And those draftsmen sound like they were real artisans.

I think a lot of what you are asking is about front end stuff, and eveyone is answering about the back end.

In the good old days people would write their designs in the form of netlists, which were interconnected library elements. Today VHDL or, more commonly, Verilog, is translated into netslists by synthesis tools. Synopsys is the dominant vendor of synthesis. Except for custom designs, like microprocessors and DSPs, they do a better and faster job than designers, and are used for ASICs universally.

This just gives the nets, but doesn’t say where they go. Place and route tools, often guided by a manual high level block layout, put the hierarchical blocks on the chip, and then interconnect them. Then you do static timing analysis to find nets that are too slow. You can’t do this until you do placement, because obviously the distance is important. You iterate a bunch, and finally pass timing.

The library elements come from a library vendor or an ASIC house, and are laid out vey carefully. There are usually a few versions of each cell, varying size and power.

More recent versions of synthesis tools take the physical design more into account, to try to get it closer to right the first time and avoid iterations.

The back end of the ASIC process, usually done at the foundry, produces a file with all the information needed top do a mask. This last step is expensive but fairly clean, so “tapeout” - which used to involve making a real tape, is the major milestone of the process. After that everyone catches up on their sleep and gets ready for the samples to come back.

Processors are a little harder. First of all, the processor team makes custom library cells. A lot of the placement and routing is done by hand, and mask designers can still make a tighter design than a tool. Intel hires lots of mask designers. So John, the profession is not dead yet. (Thought it is for ASICs.) Add to this that datapaths are often designed with aggressive circuit design techniques for speed.

Tests, by the way, are automatically generated too.

Core based designs (systems on a chip) get made with predone processor cores, cores for various I/Os, memories, etc., but there is still some synthesized random logic.

IC design involves a lot of copy-paste

You start with building the most basic components, ie a pfet and an nfet. For example, a nfet looks like this on a design software: http://www.cs.washington.edu/homes/seth/cadence/images/lab2_6.gif

Then, by copying and pasting those two, you make more complex components, like AND, OR, XOR etc. gates. A nand gate looks like this: http://www.zhangkun.net/ee477/nand.png

Then you copy and paste those gates and make even more complex devices, like an adder. An 8-bit adder looks like this: http://www.cen.uiuc.edu/~nshin/PICTS/382_full.gif

And so on…

So, there are many many layers of abstraction. Every time you want to make a new chip, you don’t have to start from designing the fets, that would be next to impossible. You use already existing building blocks.

Some pictures: http://www.technovena.com/materials/Wafers/image/silicon1.gif
http://www.tonie.net/images/sanjose2001/siliconvalley/siliconingot.jpg