Here’s an idea I’ve been kicking around in my head for a little while: A class of chips that all have the same RISC core but have multiple ‘compatibility frontends.’ The compatability frontends would work on the microcode principle: The instruction set the chip is fed gets converted to something the RISC core can use based on either ROM or very fast RAM programming. The frontends would emulate different chipsets already in use, such as Intel x86 or m68k or MIPS (an old favorite of mine :)). This would make the chips binary-compatible with those chips, while possibly gaining speed increases due to well-written frontends that take advantage of a multipipelined RISC core. And, of course, a certain opcode unassigned in the real chipset would put all subsequent instructions through to the RISC core directly.
Of course, I don’t know if it’s even possible. I don’t know if I’ve just pushed the concept of microcode a bit too far or if it would be doomed to run amazingly freaking slow no matter how well-written the frontends were. I don’t even know if it’s been tried before by some obscure company, but I don’t recall it if it has.