That’s assuming a straight line. But that never happens. Global signals move up and down do different metal layers, and jog left and right to avoid blocks of logic. No signal can make it three inches - it will get buffered multiple times in that run. Crosstalk from signals running in parallel also slows down the signal.
Designers spend a lot of time making sure that global signals are fast enough. Because if you miss one your entire part doesn’t run at speed.
I can see how 3D and 2.5D could help have an array of small chips that together form a virtual big chip. By using lots of small interconnected chips, you don’t have the same yield problems as a big chip yet you still have a lot of IC surface area. For example, instead of having 1 800mm chip, you could have 100 8mm chips which would presumably be much more tolerant of defects. You can see an analogous phenomenon in radar design where instead of having 1 big antenna, a modern radar can have 2000 antennas which form a networked array.
The main problem would be actually having those 100 chips work together to a sufficient degree for useful purposes. Isn’t interconnect speed the main performance bottleneck now?
I get that for mobile applications, taking up less surface area matters a lot. What about high performance uses like servers, industry and gaming? I thought the attraction of 2.5/3D there was more about increasing memory bandwidth by having much wider memory bus? That’s the outsider impression I’ve gotten anyway.
Could you go on about the I/O buffers?
I haven’t been paying close attention to the newest CPUs–looks like we are already back at the “size of a Buick” stage.
For most applications, the smaller the IC the better. Smaller features means less power consumption and faster operation. And small physical size is never a bad thing.
One of the few exceptions is imaging sensors. For those, the larger the sensor, the more light it collects. Figure 3 on this page shows a wafer containing just 8 full-frame (35x24mm) imaging sensors. And there are even larger examples around, for research and medical applications.
While 2.5D helps in terms of interconnect speed, it still isn’t as fast as being on the same chip. In fact the trend seems to be migrating things like memory interface hardware onto the chip. It does increase the cost.
I took parallel computing architecture 45 years ago from David Kuck. The problem then, as now, is keeping all those processors busy for high volume applications.
And partitioning a big chip is not trivial, since the caches usually get shared so that threads and processes can easily migrate across processors on the chip.
I know someone who was working for a startup which was trying to put 100 processors on a chip (with some being redundant that could be swapped in when a processor failed) but it seems to have gone bust.
Yeah, mobile is a good application since you want to keep power down. Most of the real examples of 3D chips I’ve seen have been to increase memory bandwidth. My company was not all that interested in the technology so I got most of my information from research about it, and from some papers by fabs doing it. Like AMD.
If you look at a die photo, you’ll see a ring of logic around the chip which is distinct. These are the I/O buffers, and since they have to drive very strong signals they are big and relatively slow.
These days high speed I/O is done using SerDes (Serialize/Deserialize) which puts lots of signals on one wire and self clocks. These can run at Gigaherz rates. Parallel signals like in the old days have issued due to crosstalk between signals which keeps the maximum speed down.
Serdes logic has complicated protocols and logic which finds derives the clock. There is a complicated state machine involved. I worked on this once and it was too weird for me.
I don’t know about other companies but we had nothing but trouble with this stuff. It took forever to get working during bringup. I sat and snoozed through way too many meetings where half the agenda was this stuff.
As small as you can get, but no smaller. But I have a counterexample. One chip I knew of had a chunk of logic to emulate the instruction set of an older architecture. This got reduced to decrease the size of the chip. This meant that the chip ran the old instruction set way slow. This size reduction might have wind up costing a few billion dollars.
For the OP’s question - it depends what you mean by “big enough…”? As I understand it, a transistor is an area of pure silicon doped with an adjacent(periodic table) element to make it slightly more conducive to either positive or negative. The current flowing through that area is channeled through a constriction area where the silicon around it is doped with the opposite polarity (i.e. PNP or NPN). When a voltage is applied to the opposite polarity area, it acts like a valve - a minor variation in voltage makes a significant difference to the current flow - hence, an amplifier, the original use of transistors. In digital applications, the constricting voltage complete shuts off the flow of current, since digital is on-off.
While the whole chip may be inches on a side… I am not an Electrical Engineer, but my gut tells me that the effect probably works at best in millimeters, certainly not in centimeters. Simply scaling a design up rarely works in any field due to the square-cube law - electrical, mechanical, aerodynamics, hydraulics, etc.
So that’s the question - can you scale up a simple PNP transistor and have it function effectively at 10 to 100 times normal design scale? Can you design a PNP transistor with the active area centimeters on a side? (I assume a large-scale diode, etc. is simply a large element but the doping is in layers rather than separate areas of the device?)
Yes, you can have truly Brobdingnagian transistors. They are slow, but can handle enormous current.