Whenever I read an article about computer chip technology it seems that research tends to focus on making transistors smaller and cramming more of them into a chip of the same size. That’s an understandable direction for many applications but I’m pretty sure my PC has room for a chip 3 or 4 times the size of my current one :P. Is some other technological limitation making faster chips overkill? Are the speed of chips now more dependent on limiting the distance that electrons have to travel versus how many transistors there are?
Yes, the speed of the chips does depend in part on how far the electrons have to go. Moreover, larger chips would generate more heat and heat removal has become a limiting factor, especially in laptops (where battery life is also an important issue).
Your last question nails it. The speed of light becomes a limitation. The longer the distance the electrons have to travel the slower the connections are. And, I believe, the more heat that builds up and must be dissipated. Chip speed is currently very much dependent on shorter connections and in the future will require innovative designs to get around these limitations.
Nonetheless, die sizes HAVE gotten generally larger over the long run. As observed, smaller components placed closer together yields greater speed, but you can also get more transistors on a larger chip at a given density.
As you might suspect, there are fabrication problems associated with large die sizes, as well as the heat removal problems alluded to, which is another reason nobody manufactures chips a foot square, even if they could fit terrabyte sized memory caches on them, etc.
For both speed and yield, it pays the manufacturer to cram a given design into the smallest silicon chip possible, but any IC fabricator would LOVE to be able to reliably manufacture bigger chips.
IANAComputer Engineer, but, in addition to the above, I read once that the drive for miniaturization in chips was primarily based on the fact that the cost of cooking the silicon-germanium wafers was relatively inflexible - that is, that it cost about the same to manufacture a wafer with 100 chips as a wafer with 100,000 chips on it (just the cost of cooking, not the cost of innovating the smaller chips). Because the cost of cooking said wafers is pretty high, there is a significant cost advantage to cooking a wafer with higher and higher populations of chips on it. FWIW.
Info courtesy of Mr. Parlo but he cautions this is only a rough version of the facts:
- When the chip is bigger then it needs more juice; then it heats up more; then it needs to be cooled down more; then you need a bigger fan. It’s a problem of it not being cooled down fast enough.
- The bigger it is the longer it takes for the signals to be transmitted inside the chip. With the different paths in the chip the signals can also get crossed due to different processing times. (remember we’re talking about the speed of light and a microsecond is a helluva long time.)
- Magnetic fields from each wire cause a disturbance in the signals. The more wires the worse the problem.
Heat and signal lengths (as mentioned) are definately part of it. Another limitation has to do with how semiconductors are made. Without going into too many details, basically you grow a crystal then grow different impurities into it to make the various types of semiconductors. You end up with wafers of semiconductors which have hundreds of chips on each wafer, which is then cut apart and mounted into the little case. The wafers often have flaws in them, and you’d be surprised at how many of the chips don’t work at all. If you make the individual chips larger, you end up with a higher probability of getting a flaw inside your chip, so the process favors smaller chips.
You could divide up the processing between chips. Part of the problem when you do this is that the longer the signals have to travel the slower they are. Another problem is that the more chips you have the more it costs to manufacture them, so again, this process favors a single smaller chip. There have been computers manufactured in the past that did not have all of the processing done on one chip. In fact most of the early computers were too complex to fit into a single chip at the time. Even later, there used to be things called “bit slice” processors, where each chip worked on a small number of bits. So if you wanted a 16 bit processor, you had 16 of these chips. Cost and speed drove these types of things out of the market in the 1980’s.
Smaller transistors are faster transistors. They have fewer electrons to move when they switch. So smaller roughly equals faster.
I shouldn’t have said “primarily.” I had read it was an important factor, but I haven’t the expertise to use the above word. sigh Preview is your friend…
A lot of followup questions that will really give away my degree of ignorance on things electronic:
-
It sounds like heat removal is a pretty big factor. But doesn’t the heat problem directly relate to how many transistors are packed into a given space? Does doubling the amount of transistors and doubling the space between them net no increase in processing speed because of the increased electron travel time (roughly)? Can’t we send a little jet of air directly through the chip to reduce heat?
-
How many electrons does it take to trigger a transistor into an “on” or “off” position? I would think the fewer the better. Is there research being done to lower the threshold necessary to trigger a transistor? (Go easy on me - I could be way off in my approach to even thinking about this).
-
Even more unrelated - Is chip speed the current bottleneck in video game graphics or is it human programming/art production time? If it’s the former, won’t the bottleneck eventually move towards the latter? So many questions, so little time.
The further an electron travels, the more resistance it causes in the conductor, which means you’ll make more heat. Because of this, you may even need to increase the amount of current you’re sending (so the signal doesn’t degrade too much over its trip) and that creates even more heat.
Video games are a whole different ball o’wax. Remember that on modern PCs, most of the graphics rendering takes place on a completely different chip – the processor on your video card. These things are specially designed to optimize the calculations necessary for drawing pretty 3D graphics. There are a lot of things that can affect video game performance, like how fast game data can be accessed, how fast your video and sound cards can process the data, how well your motherboard can maintain bus speeds, and so on.
Programming/art production time is only relevant to the speed of getting a game out to market, not how fast it runs. As the time gets larger and larger, companies compensate by having multiple projects run simultaniously, skewed off from each other enough to have a constant flow of games out the door. They also compensate by reusing assets from one project to another, whenever possible.
As far as video game graphics, there are two major bottlenecks: transformation and rasterization.
Transformation is the process used to take the 3d data and turn it into the screen-coordinates of triangles, along with associated data at each endpoint. Rasterization is taking that data and turning it into data at every pixel that is on the interior to a given triangle, and then compositing that information into the framebuffer.
Each process takes a varying amount of time, depending upon the exact data. A few very large triangles covering the same screen area as many small triangles will take about the same amount of rasterization time, but the latter will take a lot more transformation time than the former. Architectural design of the rasterizer will sometimes make the same triangles rasterize at varying speeds just by shifting them around on the screen. Triangles that are only partially on the screen can significantly affect transformation time.
Chip speed and bandwidth will significantly affect the transformation and rasterization time. One neat thing about 3D, though, is that it parallelizes much better than most algorithms, so you can get two to four times the speed by throwing more chips and wires at the problem. More than that, and each extra chip gets less and less effective, though, and the wiring gets significantly more expensive.
Heat is a function of the power needed, which = IV (current times voltage). If you simply scale a transistor down, the power goes up. But engineers reduce the supply voltage to offset this somewhat.
The key issue in swithing a transistor is having enough charge (electrons) on the gate to start the current flowing or to stop it from flowing. This depends, in large part, on the thickness of the gate insulator (Silicon Oxide or Nitride). The thinner the gate, the less charge is needed. But if you get to the point where the insulator is too thin (on the order of a few atoms thick), you start getting QM tunneling effects that are real reliabilty problems. This might be a big problem 10 yrs or so down the road when scaling gets to that point.
FWIW one area in semiconductors where bigger = better (apart from power transistors) are imaging chips for digital still and video cameras. Given the same number of pixels a physically larger chip and proportionally larger lenses to give the same field of view gives much lower noise levels, particularly at high ISO sensitivity, and wider dynamic range to record shadow and highlight detail. Bigger chip/lens combinations give more depth of field control but this is a matter of optics rather than electronics.
Common chip sizes are 1/1.8" (5.32x7.18mm) for most consumer digicams, 2/3" (6.6x8.8mm) for high end “prosumer” camersa and APS size (15.1x22.7mm) used in most professional DLSRs built on 35mm camera bodies. There are a few DLSRs which use a full size chip the same size as a 35mm film frame (24x36mm) but cost is extremely high and there are optical problems as film camera lenses as CCDs and CMOS don’t capture light the same at the edges as film does.
I remember the Khan episode of the original Star Trek where the old earth space vessel he is on has these enormous transistor tubes. So bigger is faster!
Anyway, just how much additional heat are we talking here? My comupter has two little fans, and I don’t even think both are needed, couldn’t it also handle another?
The real problem with “long wires” in a chip is not the speed of electricity but the charging time of the wire itself, which relates to its size and capacitance. Big wires take a long time to fill with charge until the voltage at the other end gets high enough to flip the switch. Like filling a pipe with water. It isn’t how long it takes for the first trickle to reach the other end, but how long it takes to get pressure to the other end.
Making wires shorter just means you are getting closer to speed of electricity limits, but not really close yet.
Also, yes, chips are being made of a lot more transistors which makes them “bigger” and therefore could have longer wires, but most units are kept very close to any other units they need to work with. Long wires crossing the whole chip are relatively rare. (Except for the clock signal, a very big issue.)
As I said the other day on the SDMB, making chips smaller is a multi-win situation: faster, cheaper, higher yield, etc. The real cost is in the tech to improve the fab making systems. But that has been more than balanced off by the skyrocketing demand for chips. As long as the demand keeps growing …
ftg: Just a question about your original electricty analogy…I’ve always used the idea that wires are like water pipes already filled with water and that its a misconception to think of them as being “filled up with charge”. So as soon as you push on one end, you feel the pressure on the other.
Something that no one has mentioned here is one of the most important factors of all. Extremely large die (chip) sizes suffer from what is known as “parasitic capacitance.” Unless specific measures are taken, the body of the chip itself begins to act like a plate of a regular capacitor. This can result in sufficiently large charge buildups where the resulting output can undesirably mimic a given signal within the chip itself. Special measures like trench capacitors and extra die grounding bond wires help to combat this.
Silicon wafer flaws are not such a critical issue. Considering that a finished 300 mm wafer of Pentium III microprocessors can have a value exceeding tens of thousands of dollars, the wafers must meet stringent stochiometric specifications. Huge efforts are made during the crystal pulling process to eliminate impurities, inclusions, slip and dislocation defects internal to the ingot’s lattice structure. These can include magnetic stabilization of the polysilicon melt plus counter-rotation of the seed rod and boule (the Czochralski refining process).
Some defects can be reintroduced when the ingot is sawn up. New methods such as RTP (Rapid Thermal Processing) have been designed to relieve mechanically induced stress in the cut and polished wafer. RTP involves subjecting the substrate to a very brief light pulse on the order of hundreds of thousands or millions of candlepower. Only a pulsed arc lamp can serve this function. A regular heating element does not have the short response time required to create the momentary surface conditions required for strain relief. Regular heaters would merely melt the wafer instead.
While traditional chip designs have begun to reach barriers in terms of conductor resistivity, this has already been addressed for some time now. Aluminum begins to take on resistive properties in submicron line width dimensions. New generations circumvent this issue by using metallization layers composed of copper or tungsten. Copper has proven to be one of the most problematic compounds (it is alloyed with slight amounts of silicon, gold and other materials to prevent electromigration). Copper is “soft” enough where high current densities can “knock” individual atoms downstream in the current path. Heavier metals and compounds alloyed into it to help inhibit this.
Solid state devices are extremely sensitive to ionic contamination. Silicon, by itself, is an insulator. It is brought into conductivity by the imposition of interstitial “dopant” atoms. These conductive chemicals (boron, phosphorous, arsenic and germanium) all surround silicon on the periodic chart of the elements. For this reason, they are able to be inserted into the crystal lattice structure of silicon without inducing detrimental levels of strain. Elements proximate to each other on the chart all demonstrate similarities and chemical compatibility.
The problem arises when some other ion finds its way into silicon’s crystal structure. Normally, these intentionally introduced impurities (known as dopants) are driven into the surface of the wafer via two common methods. One is thermal diffusion, which utilizes high temperatures (~500° C) to activate (or loosen up) the silicon’s lattice structure. This is a time consuming process requiring many hours and affects the entire wafer’s surface. The other favored method uses a linear accelerator’s beam line to perform what is known as ion implantation of the dopant atoms. These machines cost millions of dollars but can create extremely fine conductive structures in the silicon wafer without exposing it to high temperatures. Ion implanters literally “drive in” the dopant atoms by accelerating them to extremely high energies using many kilovolts of power.
All of these methods can be defeated by a single fingerprint. Human body oils contain copious quantities of potassium and sodium ions. With respect to silicon, these elements are extremely mobile. They are able to migrate into the wafer’s surface structure and cause significant local alteration of its conductivity. Mobile ion contamination is one of the arch enemies of device fabrication. This is where we return to the discussion of copper. Cupric compounds have been proven to be exceptionally mobile. Entirely separate fabrication facilities have been built to house copper deposition and processing tools to prevent cross contamination. This is one reason why alternative materials like tungsten and tantalum are being investigated for topside metallization. These heavier metals all contain high enough densities of outer shell electrons to easily conduct circuit impulses, even down at nanometer level line widths.
Current investigations include the fabrication of devices that can be triggered by a single electron. Polysilicon gate oxide thicknesses have finally reached their ultimate performance limitations. New hafnium and zircon oxide insulating layers are being researched. Device speeds are reciprocal to structure size. New machines that I have operated are able to deposit layers on the order of a single atom thick. While it is desirable to keep die sizes down, this is not always possible. Certain military applications demand exceedingly high processing speeds. A circuit board with several components spaced millimeters apart will have signal propagation delays that render them useless. Only single chip solutions can adequately shrink module intercommunication times sufficiently to guarantee the desired performance.
Another problem looming on the horizon is word size. For a long time, parallel transfer of word bits was seen as the ne plus ultra of digital microprocessor design. All sixteen bits were transmitted simultaneously along a group of sixteen individual parallel conductors and arrived at their intended register. Parallel transmission remained at the forefront only until recently. New USB protocols are intended to address this issue. When you are clocking a processor at gigahertz rates you encounter what is known as “settling time.” All bits must arrive at the intended location within less that the duration of one processor clock cycle. If a bit is in an indeterminate state it will introduce a single bit error. This can be corrected utilizing standard parity code error detection techniques. Parity functions are unable to sense double bit errors in this same situation. Now that processors are evolving into 64 and 128 bit word sizes, parallel transmission is no longer viable.
In the early 1980s, Motorola redesigned one of their four bit microprocessors (used in toasters and low level applications) over from parallel to what is known as serial transmission. This is where all of the word bits travel down a single wire and the binary word is reconstructed at the arrival point using a conversion buffer or shift register. The Motorola designers were able to reduce the footprint of their processor on the order of ten to fifteen percent by doing so. This means that, without implementing any other yield improvement procedures (i.e., cleaner machines, higher purity chemicals, etc.) they were able to get an increase in the number of useable chips from the same wafers using the exact same fabrication methods. The cycle time was slowed imperceptibly (especially for such undemanding applications) due to decrease in the die size. The dies were smaller because the four bit parallel conductor paths were now condensed into a single line using the serial transmission technique.
This is the design barrier that modern circuit engineers are now facing. It is literally impossible to hope that 64 or 128 different bits, often sent from different regions of the chip, will all arrive within the necessary single clock cycle time limit. New serial word transmission methods are being used to once again reduce the footprint or “real estate” that the die’s active devices occupy. This is not so much to shrink the circuit’s overall dimensions but, rather to create new elbow room for additional processing or memory capacity.
I hope this clears things up.
Zenster
Somewhere around this house, I have a piece of wire, about 11 inches long, given to me years ago at a speech by a wonderful, incredibly impressive lady, the late Admiral Grace Hooper. She called it a microsecond, because it was the length that electricity could travel in a microsecond. It’s quite a powerful visual aid, to look at this piece of wire that goes from about your wrist to your elbow, and realize that is the size limit for a CPU to operate at 1 MHz (which was high speed back then). Given todays processor speed, the maximum size is probably smaller than your thumb!
KidCharlemagne, if you want to see an interesting life, do some searching on Grace Hooper. She started during WWII, and was one of the first people to work on computers, and one of the first to work on computer languages. She discovered the first computer “bug”. (An actual moth , which she swatted & then pasted into the Univac I logbook.) She probably created the first computer language compiler. She is referred to as the Mother of COBOL, and she concieved not only the ideas used in COBOL (and in most languages since then), but the very idea that a computer program language could be written that would run on different brands of computers. You may find it hard to imagine a world in which the program that runs on a Dell PC won’t work on a Gateway or a Compaq, but that was the way all programs were before her. She retired from the Navy at age 80, and promptly was hired by a computer company (DEC, later Compaq, later Hewlett-Packard/Compaq). She was also great at coming up with neat quotations. Like:
“You manage things, you lead people. We’ve gone overboard on management and forgot about leadership.”
“It’s easier to get forgiveness afterwards than to get permission beforehand. So just do it, then apologize later.”
“Humans are allergic to change. They love to say ‘We’ve always done it this way.’ I try to fight that.”
Actually, what you have there is a nanosecond.