I am trying to make a 1kHz to 20kHz VCO to use in a PLL for an electronics class. The part above is the function generator we have to use. It hass all the major pieces of a PLL built into it.
This is the way I understand a PLL working and I wanna make sure I understand this corectly before I ask some questions:
External input signal and output signal from VCO are fed into a phase detector, which is basically a signal multiplier, which is also included on this chip.
The multiplier gives you 2 different signals. One is the sum of the 2 and one is the difference of the 2.
You take a LPF and cut out the sum signals. Leaving you with the difference of the signals.
If the difference is zero then everything is great and the PLL just presses on.
If the difference is positive then the PLL speeds up the VCO to match the input signal.
If the difference is negative then the PLL slows down the VCO.
Now, looking at that data sheet I do not see how to configure this thing to run the VCO at 1-20Khz.
Why are there 2 different pins for timing resistors and 2 pins for timing capacitors?
I am unsure what formulas to use to set this up to run at a desired frequency. Do you take the 2 timing caps and match them with the 2 timing resistors using 1/(RC) to equal the 1K and the 20K? I do see that formula mentioned on the FSK diagram on that page, but I am not sure that that applies in this case.
The write up we have in the class for the lab shows a half wave rectifier being used to cut out the negative swing of the output of the PLL. I am not sure what the putpose of this is, though I think it is to have only a positive current feeding back into the VCO for the PLL.
Can anyone point me in the right direction on this thing?