Right now there is a race to be smaller and smaller when it comes to transistors(?) in the semiconductor industry, although we may be nearing the end of Moore’s Law. Used to be 10nm, now going down to 7nm, and now 3-nanometer is expected to come online in a few years. Some speculate we may get into the realm of picometers.
Is it a matter of proportionally better performance - that 3nm gives you twice the performance of 6nm, since you can squeeze twice as many transistors onto a space?
It’s not just transistors, but how long the signal paths have to be. If everything is smaller, including both the transistors and the signal paths between them, then the propagation delays from one stage to the next in the semiconductor are much smaller.
Smaller transistors also put out less heat, and when you are trying to cram as many transistors as possible into a tiny package, getting the heat out can also be a huge limiting factor. Sometimes things are spread out on a chip (with the expected loss in performance due to both transistor density and signal propagation) just because they can’t get the heat out of the chip quickly enough to prevent it from frying itself under load.
Semiconductor wafers also have a huge failure rate. Silicon is grown as a crystal, and it is very easy for large silicon wafers to end up with cracks. The larger your chips are, the more likely they are that one of those cracks is going to end up going through part of them. So the smaller you make your chips, the higher your percentage of good chips.
Probably not all that much, considering that the main computing bottleneck is usually memory bandwidth, not the processing itself. If you want to look at increases in performance, there may be more potential in things like HBM than 3nm.
This part is sort of true but is less relevant for transistor size. There’s the size of the chip packages themselves, which hasn’t really changed too much in a while, and there’s the size of the transistor gates, which has gotten smaller with time.
It is true that you can probably get some modest yield improvements with smaller packages but using the same transistor gate size. But this can’t be changed arbitrarily.
It is absolutely not true that smaller transistors improve chip yields. The opposite seems to be true in practice. Smaller gates require tighter tolerances and newer technologies and partial or complete failures are high. There are a variety of ways to work around it, though.
This is going off my now decade out of date experience, but modern yields are poor by historic standards. Nearly every component will have some issue, but they may be sufficiently minor to still pass spec. Still, there are ways around this to improve the overall yield.
One is by marketing products by different performances classes. Components that are overall functional but which have parts which do not function at spec or do not function at all can be sold under a different class with lower specs.
Also, there is some redundancy in the design itself so that failures can often be worked around or even fixed after fab.
And then there’s just always accepting that yields may be poorer than hoped. It’s part of the process to expect that X% (and X can sometimes be higher than 50) of components on a wafer will need to be junked. This value tends to get lower with more mature or simpler components but may be shockingly high for the latest/greatest processors to be used in the latest phones or supercomputers.
Getting the yield to an acceptable level is up to the engineers and determining at what level a particular yield is uneconomic is up to the accountants.
It’s actually closer to 4 times (not exactly 4 though) as many transistors in the same space - it’s roughly by area, not linear measure, though they’ve started branching into the 3rd dimension a bit as well nowadays.
Smaller transistors require less electricity to do their work. So they switch faster and each generates less heat.
But by packing more of them closer together there isn’t always a net improvement in producing less heat per square cm, esp. when trying to bump the clock speed up.
While decktop PC CPUs no longer have the big clock rate increases of days of old, there’s still some room for improvement with smaller things like mobile devices.
The big issue for a lot of mobile devices is battery use. So smaller transitors draw less power. That’s good. But there’s a lot more of them on a chip and they’re running faster. That’s bad. But you get your choice of topping! That’s good.
The toppings contain potassium benzoate.
I’ve worked in electronic testing for over 30 years, have some fame in the field, and that’s the funniest thing I’ve ever heard.
The opposite is true - the smaller the feature size, the more defects cause failures, and the lower the yield. Obviously big chips have lower yields also.
The primary failure mode is not big cracks running through things, trust me.
Also, design rules have to be tougher at smaller feature sizes. A signal line going around the corner with some degree of excursion might be fine at 10 nm but causes a short at 5 nm.
And clean rooms have to be cleaner at smaller feature sizes, since smaller dust particles can cause failures.
While a smaller transistor might be thought to put out less heat, they actually leak current - the leakier the faster. I worked on large processors at 5 nm nodes, and they were very hot and sucked up so much current that getting power supplies for burn-in was a real problem. You couldn’t run them at speed during wafer probe because you couldn’t supply enough power to them.
It is expected that yields will go down at new nodes. They come up over time as problems are worked out.
And people don’t tend to migrate existing designs to more aggressive nodes. You use that capability to add transistors - to be used for more on-chip memory or more cores. So I’ve never seen a direct comparison.
Yields depend on the product and the maturity of the process. Something small in a well-understood process node is going to have excellent yields. A new gigantic processor in a new process node will have relatively miserable yields. I owned this information for my company.
Which has been done for decades. If you build an 8 core processor, you can sell a cheaper 6 core version to make money for parts with a few bad cores.
I knew of one case where the cheaper version was more in demand and the yields were good, so some good cores got disabled to supply the cheaper version.
All decent sized embedded memories have redundant rows/columns to allow for repair during fab. Trust me - yields would be unacceptable without this feature. There is also the concept of built-in self repair, which allows repair to be done in the field after the part goes through power up. I’m not sure how much this gets used, but it is well understood.
Our volumes were low enough that we didn’t care about yield all that much, and I clearly can’t say what ours was, but 50% yield would be a disaster even for us.
There are a bunch of software tools that looks at fab data and analyzes it looking for problems. I wrote one of these myself for my company, but my stuff was used more in bringup than in production. None of the commercial tools are targeted for this.
I didn’t catch you were talking about wafer cracking. Fabs have ways of detecting this before you add any active components. I never saw a single case of failures due to bad wafers. I did see cracking issues but they were introduced later.
Fabs put measurement hardware on the wafer between scribe lines. I don’t think they can detect cracking (they don’t have to) but they are used for testing before a lot of money is put in, and we rejected entire wafers if enough of these instruments failed various measurements.
From https://en.wikichip.org/wiki/technology_node
"Historically, the process node name referred to a number of different features of a transistor including the gate length as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it’s what the leading foundries call their nodes.
Since around 2017 node names have been entirely overtaken by marketing with some leading-edge foundries using node names ambiguously to represent slightly modified processes. Additionally, the size, density, and performance of the transistors among foundries no longer matches between foundries."
Can I go now?
Thanks for the answers.
So what is the “TL: DR” answer to the oft-asked question these days: “can gate length really shrink in this industry all the way down from 3nm down to mere picometers, and if so, what is absolute bottom?”
(Although I see road lobo’s cite that it’s not necessarily about gate length anymore by name)
The tl:dr is “The industry sure as hell would love to keep selling new generations of chips and faster chips definitely would be nice to have but nobody knows for sure if even 3 nm–much less smaller–is feasible as a stable, useful, economically plausable design and people promising dates for it’s delivery are making pie-in-the-sky guesses.”