Hey, I’m working on a logic design problem, very simple actually, but harder than I’d want to do by hand. When I was in school we used ABEL and XILINX, but now that I’m out I have no access to any design programs. Does anybody know of any free or shareware programs I can use to just write out some simple logic code and then optimize it?
What language?
Audiobottle, you don’t say what devices you plan to implement the logic designs on, but you mention that you used Xilinx parts at school.
The Xilinx ISE WebPack is freely downloadable, although you have to register first.
It includes ABEL, VHDL, and schematic entry for Xilinx CPLDs, which I assume will fit your requirements. There is also support for all but the largest devices in the Xilinx line of FPGAs.
The free WebPack is missing some features compared to the Xilinx BaseX ($695) and ISE Foundation ($2495) software packages, but if all you want to do is some simple logic, it’s way more than sufficient.
At opencores.org there are links to open source design ware, but I have absolutely no experience with them, and make no guarantees. What are you designing to? If it is for an FPGA, the design ware from the company is probably best.
If you try the open source CAD tools, let us know how it goes.
If you’re trying to simplify truth tables, there’s a very powerful freeware tool available called (I believe) Espresso.
It will take logic functions like
abcde + bcdfg + acfg + bdf + ag
and spit out a handy answer (though you have to convert the logic fuction to a simple 0 and 1 format).
Here’s a website with instructions: http://www.csc.uvic.ca/~csc485c/espresso/instructions.html
(My years in Electrical Engineering finally are paying off!)
Sorry I wasn’t more specific. It’s for a very, very simple logic problem that just has a lot of states I didn’t feel like writing out by hand. Espresso sounds like it might be right up my alley. I didn’t realize they had Xilinx for free (sort of). I might go with that, but I have terrible memories of clicking on something in Xilinx and watching the entire thing disappear without a trace.
Thanks guys! And no, no FPGA stuff. Just a simple logic gate to use on a counter and transmitter stuff.
Okay, back again. So here’s my question. It’s been a while since I took my logic design course, so I’m not sure if there’s something that fits this bill.
I have a counter. I want it to turn on a transmitter for x cycles, and then off for y. Obviously I can go through and do a state table for cycles 1 to x so that it outputs a high, and then from x to y so that it outputs a low, and then at y so that it clears the counter. However, this seems like a major pain in my ass. Instead, I’d rather have it flip a switch when it reaches state 0, flip it again (the opposite direction obviously) when it reaches x, and then just have it clear at y, thus making my state table only have 3 true outputs instead of a ton. I know there must be something really easy for this, and it’s really bothering me that I can’t think of what I could use.
A flip-flop should do the trick, I would imagine.
Flip flop! That’s the thing I was thinking of. I guess with all the Kerry = flip-flop going on in the media, it pushed the old association right out of my head. Thank you Joe Random!
Heh. You have no idea how hard is was for me to resist a Kerry reference in my post.
It also occurred to me that you could get the same effect with a latch. Depends on what you have handy (or which design simplifies to the fewest gates).
You bet. I’ve certainly learned enough from reading the SDMB that it only seems fair to help others in turn.
Oops, one more question. Sorry to keep bringing this up. So say I can do what I laid out a couple of posts ago. What will be outputted by the states that I don’t define? Does it matter if I don’t define them?
Put in a better way, is it easier for me to design this:
I have 15 bits, and out of all the states I only want three of them to output high.
Or this?
I have 15 bits, and on X number of states I want it to output high, Y number of states I want it to output low?
Wait, nevermind, I think I answered my own question. Of course scenario 1 is easier since the logic program will automtically make all other states 0.
I’m sure I’ll be back with more questions later.
I’m not too clear on what the difference between a latch and a flip-flop is. From what I see, the SR flip-flop is the same as the basic SR latch.
My other question regarding the flip-flops is how do you initialize it from the start? Do you have to initialize it at all?
The answer is that latches are evil. They get instantiated by mistake all the time with VHDL and verilog. They create problems for scan test. In general they are best avoided.
A latch will pass the input thought to the output when the enable is high and hold the value of output to be what it was when the enable went low.
Flip flops on the other hand sample the input data on a clock edge.
So the difference is a flip-flop is a clocked latch? Otherwise same functionality?
Yes they have the same functionality except where they are different.
Okay, I think I’ve got my design figured out then. I just have to implement it. Thanks for your help again!
That was probably a little snarkier than needed.
They are similar in that they hold a state. They are different in how the state is loaded. I would howver say the functionality is not very similar.
There’s not too much difference. A gated S-R latch has three inputs: E (enable), S (set), and R (reset). When E is high, S will set the output, Q, to high (and the inverse output, Q’, to low). Pulling R high will do the opposite. When E is low, the output will be unchanged no matter what you set S and R to. Note that you can set E, S, and R all to high, and you’ll get both Q and Q’ outputting low, but that’s an unstable configuration, and when you remove voltage from E, you’ll have no way of predicting what the latch output will stabilize to.
A J-K flip flop (and no, the J-K doesn’t stand for a John Kerry) has inputs for C (clock), J, and K. When J and K are both set to high, transitioning C from low to high (or from high to low, depends on whether the flip-plop is rising-edge triggered or falling-edge triggered) will cause the Q and Q’ outputs will flip values. A pulse on C when J is high and K is low will set the Q to high, and when J is low and K is high, it will set Q to low. Setting both J and K low (or leaving C low) will latch in the current Q value.
So really, both devices will do what you want. For simplicity, I’d go with the flip-flop. Since you said you have a counter, I assume you already have a clock signal, so just AND your clock with the counter states that you want to change the output, and feed that into the flip-flop’s C input. Of course, make sure to pre-set the flip-flop.
Actually, you might want to solve your states to determine if it would be easier to differentiate between on-states and off-states, or between toggle-states and non-toggle-states. Since you’re wanting to leave the output high for a number of sequential states, and then low for a number of sequential states, it’ll probably be easier to differentiate between on-states and off-states for your switch, and just latch in the correct value every clock cycle with a S-R latch.