I’ve been asked to come up with a device that can be used as a sort of “quiz buzzer”.
The idea is that the moderator will press a button which will “release” the contestant’s buzzers. The contestants will then press their buttons and the first one to press, wins.
The second part was easy enough. JK flip flops, “cross linked”, to lock the others out via an “and” gate.
The first part is giving me fits, the “press a button to release” part.
The goal is that if a contestant presses their button early, then they don’t get to play. The moderator must “enable” them first.
Every design I’ve come up with suffers the same problem. If the contestant presses their button & holds it down, the moment the moderator releases them, they ring-in.
I want the order to be:
contestant then moderator == lockout
moderator then contestant == competing
Make sense?
Any help? I’m just missing it “by that much”…
Standard 74xx CMOS logic gates are available, we’re feeding the same 1000 Hz clock into everything.
While I’m at it, 5v as chip voltage, the logical 1’s are hovering in the 3.5v range, is this normal? Any problem with cascading at this voltage?
-B
(and, No, this isn’t a homework assigment - I’m an old guy that hasn’t used his BSEE degree in 18 years).
One solution: Use a second flip-flop or latch to determine lockout. The contestant’s button signal X is demultiplexed by the moderator’s ENABLE into lines X0 (=X&~ENABLE) and X1 (=X&ENABLE), sending X0 to JK1 and X1, through an AND gate, to JK2. JK1 is the lockout-state flip-flop; its negated output ~Q1 is ANDed with X1 and the negated outputs of the other contestants’ flip-flops to send as input to JK2. Q2 controls the contestant’s lamp. (The RESETs of both JK1 and JK2 are connected to the moderator’s RESET button.) Now if the contestant pushes his button when ENABLE is low, JK1 gets set, disabling any later signals on X1.
3.5V high is pretty normal for TTL with a totem-pole output stage.
The biggest real-world annoyance with your construction is likely to be with cheap switches and flaky connections.
Why not have the moderators button be a switch? Depressed completes the circuit for “buzz in” and undepressed completes the circuit for “lockout”. Thus, if a player hits his button when the button is undepressed he gets locked out becuase that is the circuit enabled. If he hits it while its depressed it completes the buzz in circuit and he gets to play.
Yes, but it sounds to me like he wants an early button-push to disable all later button-pushes by that contestant, not just to ignore early pushes. This requires another state bit.
However, using clockless edge-triggered latches instead of clocked flip-flops might be a good idea. This reduces the tie timewindow from the clock period to something like the roundtrip signal travel times (probably us or less).
True CMOS gates should be close to 5V out for a logic one. Are you sure you’re not using TTL 74xxx series gates?
Nowadays many people would use a PIC microcontroller to do the entire thing. You could select the smallest one with enough I/O lines, and write the entire thing in a page or so of firmware, and probably be about the same cost.
Good point; I hadn’t noticed that. The title says TTL but later it says CMOS. I think they are usually interchangeable in practice (each input accepts the other’s output ranges), though.