I am writing this VHDL to make a 7 segment display driver for school. I am having problems with the selected signal assignment at the bottom of this code. It keeps giving me an error that says that “choice value length (4) must match selector value expression length”. I have been looking at this for an hour now and can’t figure out what I Am doing wrong.

The only part of the code that is not compiling is that last piece. All of the IF/Then stuff works fine. I included all of it in here just incase someone wanted to see it

**

library ieee;

use ieee.std_logic_1164.all;

ENTITY ssd IS

PORT(

b0, b1, b2, b3 : in bit;

a,c,e,f : out bit

);

END ssd;

ARCHITECTURE operation OF ssd IS

begin

process (b0, b1, b2, b3)

BEGIN

```
IF((b3 AND b2) = '1') THEN
c<=(NOT b1 AND b0);
ELSIF (NOT b3 AND NOT b2 AND NOT b0 AND b1) = '1' THEN
c<= '0';
ELSE
c<= '1';
END IF;
end process;
process (b0, b1, b2, b3)
BEGIN
IF ((not b3 and b2)= '1') THEN
e<= (b1 and not b0);
elsif ((not b1 and b0)= '1') THEN
e<= (b3 and b2);
elsif ((b0 and b1 and not b3 and not b2)= '1') THEN
e<= '0';
else e<= '1';
end if;
end process;
process (b0, b1, b2, b3)
BEGIN
IF ((not b3 and not b2)= '1') then
f<= (not b1 and not b0);
elsif ((not b3 and b2 and b1 and b0)= '1') then
f<= '0';
elsif ((b3 and b2 and not b1 and b0)= '1') then
f<= '0';
else f<= '1';
end if;
end process;
*WITH b0 & b1 & b2 & b3 SELECT
a<= '0' when "0001",
'0' when "0100",
'0' when "1101",
'0' when "1011",
'1' when others;
```

END operation;**

The part in italics is the part that I am having problems with. I think I may be referencing my inputs wrong.

Anyone have any idea where this simple error is at?

Thanks.