Those are called “scribe lines,” and are under .1mm wide.
So, some waste, but not a huge amount.
The real challenge is back-grind. Shaving off all the excess on the back of the wafer. I do NOT envy the guys who have to work back-grind.
Not even all of that is waste, since the fab puts in some instrumentation in the scribe lines (like 9 per wafer for us, but other products could be different) to monitor the process. We got some but not all this information.
Yeah, we used to put alignment chevrons and some test patterns in the scribe lines, but the test guys didn’t like the fact that they couldn’t run burn-in on their test structures.
Huh? Do you burn in wafers? Burn in is to accelerate reliability failures, and since those structures aren’t going to the customer, why do they think they need to burn them in?
To do parameter drift testing after exposure to heat and voltage stress. But, I was just the e-beam litho guy, so I don’t know exactly what they were looking at. We used to have dedicated test die that would get packaged and tested separately.
The “array of sensors” makes me wonder about how a camera (or other device) which uses an array of sensors could be different in capabilities from a camera which uses 1 big sensor.
For radar, the switch from mechanically scanned antenna (1 transmitter/receiver and amplifier/phase shifter, much like a typical camera with 1 sensor) to passively electronically scanned array (1 transmitter/receiver and many amplifiers/phase shifters) to active electronically scanned array (many transmitters/receivers and amplifiers/phase shifters) has been a major boon. What would be the advantages of something like that in a camera or other non-radar device?
The NVIDIA GV100 is 815 mm[sup]2[/sup] and has 5,376 “cores” (though each of these cores is much less powerful than an x86 core).
We designed really, really big chips, so we had lots of instrumentation on-chip for this. We definitely tracked parametric drift after burn in. That was some of the data I collected.
But that instrumentation was different from that put in between chips on the wafer. We didn’t run test chips during production, but we had them to prove in new cell libraries and new processes. And to zap at Los Alamos.
When I was in the business (decades ago, now), EEPROM and EAROM where the big things for us. A lot of testing was done to characterize oxide and nitride leakage and mobile ion contamination from processing and packaging. Most of the chips were pretty small (especially compared with the monsters being made today).
I worked in the industry for 16 years (left a few years ago). I was told by multiple production engineers that the step from 300 to 400 made handling by humans much more difficult and production would have to be retooled around more robotics and automatic handling. Wafers were generally processed in cassettes (also called boats by old timers) holding 25 of them and were manually loaded onto many production tools. The 300mm cassettes were already pretty large and unwieldy to handle.
Note that while 300mm doesn’t sound very large (about a foot), the machines that process those wafers are quite large (think truck sized) and extremely expensive - scale that up 10X and the equipment would be have to be much larger (maybe small airplane sized?) with huge cost consequences for not only the equipment but for the fabs as well.