The advantages of using a smaller node is require less energy, producing less heat and being able to fit more transistors on a silicon wafer, right?
I’ve heard many times that going to a smaller node means lower processing power costs. Is this chiefly because of the greater number of transistors per wafer?
If so, it would seem that the cost of wafer is a major part of chip costs. I’d have thought that R&D, plant/machinery would be the main costs of chip production followed by production line labor with the cost of silicon wafer being near the bottom.
Can someone fight my ignorance about the costs of chips and processing power?
The business is probably pretty stable on those costs now, but you are comparing the fixed cost of a wafer to other variable costs. The company can stop their R&D and still make chips, but they can’t stop using wafers. Anyway, you should get some very good responses about those costs in the industry right now from some Dopers.
I worked in the IC industry for over 20 years and I honestly don’t understand the question. What do you mean by “node”.
But if you’re asking about the cost of the silicon wafer itself, that is dwarfed by the cost of building the manufacturing facility which is measured in billions of dollars. Not to mention all the R&D cost as you noted.
Going to a smaller die size give you greater yield in the manufacturing process and less waste
The old adage is that the first chip off the line cost hundreds of thousands, the second costs a nickel. That’s old number. Both are larger now, especially the first.
But still it highlights the relative costs. Getting to reliable production of a new chip is incredibly expensive, from then on costs are relatively negligible.
Note: by “node” I presume you mean “transistor” (although chips have other types of components).
If you make a transistor smaller:
It uses less power.
It switches faster.
It takes less time to communicate with nearby components since they are closer together.
You can fit a lot more transistors into the same chip acreage.
But as the transistors get smaller, you need to develop significantly new methods for doing that. Smaller masks require higher frequency sources, the elements are more “fragile” in that it doesn’t take much to cause a fault so tolerances are an immense issue, more layers are required, etc. (And making them faster and denser makes heat waste a big problem.) To do all these requires building new fabs, which are multi-billion dollar plants. About the most expensive things private companies build.
I worked in the Semiconductor industry too, and had never heard of the term “Node” until the SDMB. It means “technology step,” like 18nm, from 23nm.
As for the OP, he needs to define whether he’s interested in production cost or the the entire development/marketing/production/facilities cost amortization.
The cost of the actual silicon wafer is not insignificant, but also not the dominant cost. There’s been research in reusing wafers. Since the components live in a very thin region at the top of the wafer, in principle you can slice off the active part and still have ~99% left, which you can then reuse. The thinned part can then be mounted on something less expensive.
The major cost of wafers really comes down to the increasing complexity of each node (I’m surprised that the IC heads here haven’t heard this term). For instance, the small nodes require a technique called double patterning. This offsets a second mask slightly so that when the two are lined up, you get finer detail (hand-waving over the details here). But of course this roughly doubles the production time since you have to project two masks at each step instead of one.
Another example is immersion lithography–the placement of liquids between the lens and wafer to get a higher numerical aperture. But this again requires extra steps with extra cost. Every new process node has required more and more of these tricks.
The transistor costs are irrelevant except inasmuch as smaller transistors require finer details and those require these advanced techniques. The equipment costs I’m not sure about; I don’t think they’ve skyrocketed, but what’s certain is that the equipment is used for longer on each wafer, so it gets amortized over fewer wafers during its lifetime. Alternatively, you need more equipment to get the same production rate.
We aren’t there yet, but the way the cost per transistor curve is going, it looks like we’ll reach a point where the new nodes won’t be cost effective. The extra density won’t cover the additional production costs.
One other thing–current lithography uses 193 nm lasers. This is an established technology, with (relatively) low costs, and its lifetime has been continually extended with tricks like what I mentioned above. Smaller wavelength lasers/optics do exist, but they’re very expensive and manufacturers have been resistant to switching, since the current stuff is still good enough. There’s also electron beam lithography, which is also extremely expensive and slow (though useful for prototyping).
Node is pretty standard terminology today, not just at Intel.
You can’t exclude amortization of the fab costs from the cost of the wafer. Really old technology, made in process lines which have been paid off, are cheap. But part of the cost of newer technologies is in the capital plant. I don’t know how many process steps wafers go through these days, but there is a long time between tapeout and silicon for newer geometries. Measured in months. Keeping that going isn’t cheap either.
For the same process, smaller dies have higher yields - both in more dies per wafer and fewer defects per die - and are cheaper. I took the OP to mean smaller chips from more aggressive technologies shrinking feature sizes. These aren’t cheaper.
I can’t give you any real numbers, of course. But there are a lot of factors, depending on the size of the chip, the expected volume of sales, the technology, and lots of other things.
If this is a microprocessor design, R&D is going to be a big factor. But lots of chips are assembled from preexisting pieces called cores or IP (for intellectual property) which you license from someone. ARM processors are the best known, but there are cores to do all the standard interfaces. So a chip made out of this with a little bit of custom logic to tie it together will be a lot cheaper.
And of course if you sell a lot of parts, the cost of the design is relatively smaller than if you don’t sell many.
The next, and usually biggest, factor is yield, which is the percentage of chips on a wafer that are good. Say your wafer cost is $10,000, and you have 1,000 chips on it. If your yield is 50% you get 500 good parts and your cost per chip is $20. If you have 80% yield you get 800 good parts then the cost per chip is $12.50. So you see why we spend so much time improving yield. In fact, processes have design rules, for instance requiring that signal leads are a certain distance apart, to reduce the impact of defects and improve yield.
And new technologies are more expensive, and often have lower yields, and require more work by process engineers, especially if your part is a process driver (one of the first parts through.)
So small chips made with old processes are dirt cheap, and large chips made with new processes can be very expensive.
And we can throw in field programmable gate arrays (FPGAs) which can be programmed in the field (duh) so one FPGA template can be used for lots of customers and designs. They are less compact than custom chips, but the design time is much lower, especially since you can program one, test it, reprogram it to fix bugs, retest again. Which is more like software.
Another route to higher margins is to disable the defective functional parts and sell the chips for slightly less. Suppose you have a chip with 16 processing units, which take 75% of the chip area, and you’re getting 50% yields. Instead of simply getting 50 parts that you can sell for $100, you get another 37 parts with 94% performance (since they only have 15/16 units working), which you might sell for $80. The remaining parts have defects in non-redundant units, and can’t be salvaged–the smaller a fraction you can make this, the better the effective yields.
This is very common in the GPU industry. You’ll see several different products with the same chip, but different numbers of enabled functional units.
What kind of frequency are consumer-level 14nm node chips expected to reach? How about all the way to the 5nm node expected in 2020-2021?
Even as nodes have gotten smaller, CPU and GPU coolers have grown bigger and more powerful. Wouldn’t the opposite be expected as the nodes get smaller?
And one large chip is more powerful than a cluster of small chips with the same node, microarchitecture, number of transistors and total die size?
Since older nodes tend to be much cheaper, I’d have expected GPU nodes to simply use the last-generation CPU node. It doesn’t seem to be that way. Nvidia’s GPUs switched to 28nm around the time (2012) that CPUs switched to 22nm.
When manufacturers don’t have enough of the botched version of a chip, do they kneecap good ones?
My first thought would be that the lower-end version would go up in price and the high-end version would go down in price but that doesn’t seem to have happened with the GTX 970/980.
The GTX 960 Ti will come out some time and it’s based on the GM204 like the 970 and 980. Did the manufacturers warehouse badly botched GM204s until they could turn it into a new product?
That’s all part of yield. It is pretty much essential today to repair big memories, like caches. I have the numbers on this, but can’t share them.
There was one startup which was designing a 100 core chip (it went bust) and had spares that were not user visible. Some companies sell 8 core or 6 core versions of the same chip, the six core version being ones with one or two cores defective.
Except when there is so much demand for six-core versions that they sell eight-core versions with two good cores disabled.
Smaller nodes and bigger chips running faster have more leakage, and more power requirements, and thus more heat. Information theory - the more information, the more energy.
The problem is inter-chip communication. Going through buffers slows it down, though serialized signals are pretty fast, but you are sending signals further, which takes longer.
Which node to use is a complicated decision based on cost, competitive pressure, process risk, and a bunch of other stuff. But we’re staying a bit longer at a node than we used to.
I’ve seen it happen.
When I was at Intel they put out a 168 MHz version of a Pentium and a 175 MHz version seemingly weeks later (exact speeds are fuzzy to me.) Whenever you work at a microprocessor house you accumulate gifts with dies embedded - Intel sold jewelry. People joked that the jewelry had working 168 MHz parts.
As I’m sure you know, that could be just different bin speeds. Or a tweak in the process to skew the bin-outs to the higher speed. For those not familiar, a manufacturing line is going to put out a distribution of speeds even on the same chip. After testing, you might “down bin” the slower ones and sell them for a lower price (or up-bin for a higher price). Not sure if they still do it, but in the old days, the different chips were literally spit out into different bins (boxes) at test.
IC manufacturing has 3 main parts to it: Wafer fab (which is what we’re mostly talking about) that takes the longest (measure in weeks), then packaging (measured in days or hours) and test (also measured in days or hours). It’s the final test that determines how the chip is going to be labeled.
Are they gimped with code only or do they use tiny little hammers until the chips are proper scoffed up?
It seems like it really would be a failure of marketing (not just sales but marketing as a whole) if it’s their best interest to make chips perform worse.
When do you think we’ll see consumer-level chips that boost to 5GHz without overclocking or consumer-level chips that can be overclocked to 6GHz?
How do you think GPU performance will be affected by HBM and the switch to 14nm or 16nm? Was video memory bandwidth one of the main bottlenecks in improving GPU performance this generation?
And Pentiums had lots of speed bins. But these two were so close together that marketing-wise there was no reason to bear the expense of two product numbers, let alone the confusion this would cause.
Here is how you do speed bumps in this context (and the very last person doing this for Pentium transferred into my group.) Chip speed is determined by the slowest of the zillion paths between flip-flops. (Also my the speed of memories, but let’s ignore that.) If you crank up the clock speed, eventually one or maybe a few paths will fail even in good chips. If you find that path, or set of paths, you can figure out why it is slow. Sometimes it is layout - a crooked path, and sometimes you can fix it easily by adding faster buffers or something. Accumulate enough of these, and you can do a mask change that will lead to a faster part.
I don’t think minor process tweaks will do it, and in any case you don’t tweak working process for fear that it will break something else. Intel practices “copy exactly” where all fabs do things in exactly the same way for the same process, so you don’t want to mess with small changes.
I didn’t mention package cost, but that is an important point. One reason you put so much effort into wafer test is that the packages of advanced microprocessors are damn expensive. And package test may not be something you do very quickly. For high reliability parts you need to test at different temperatures, and if you burn-in the parts you test before and after. For the stuff I’m doing now it is more than a day. We track this information so closely that I can tell when the operators go to lunch.
Package test is not redundant. In some cases you can’t apply enough power to a part at wafer probe to let it run at speed, and so speed test has to be done after it is packaged.
As for test time, it depends on what kind of test you’re talking about. Wafer and package test had better not take days. Reliability testing, to qualify a new product, does take days, and if you are doing system test that can take a very long time.
Not unless you connect the power supply for your spa to your PC. And considering the drive is for lower power parts, not likely to happen. If we still used desktops, maybe some day, but most consumers would like their laptops to run unplugged for more than half an hour. And the heatsinks on these things are immense. Plus there is little consumer demand for this kind of single thread speed. If you need it for a short time, doing your computing in the cloud is going to make a lot more sense.
I’ve worked on one graphics ASIC, but on something that didn’t require me to understand how it worked, so I don’t know much about the details of GPUs and wouldn’t want to say anything about where they are going.
Well it depends what you define as consumer. Graphics / Video / 3D artists certainly need the extra thread speed, not everything we do can be easily multi threaded. Its consumer at least in the since that we mostly use high end desktops from Apple / HP etc Long gone are the days of exotic purple machines from Silicon Graphics costing over $100,000 US.
Intel’s i7 Extreme Editions are listed in their “consumer” roadmaps and considering a Devils Canyon CPU was released 2 years ago with base clock of 4.0 Ghz and turbo to 4.4 Ghz then I would hope we can eventually see Intel CPU’s with 5.0 Ghz base speed at least for the enthusiast / and media creator markets.
That’s what I was thinking of. Some games really can use more single-thread performance. Also, some forms of media creation like calculating global illumination relationships are apparently difficult to parallelize and can take days to compute a level. Moving a small object in a photorealistic visualization scene can also add hours or days.
Am I correct that anything that is easy to parallelize can be assigned to a GPGPU like Nvidia’s CUDA cores which leaves only the difficult-to-parallelize stuff to the CPU which means there can be great benefit from high single-thread performance?
If not, what is it that would make sense to assign to a multicore CPU but not a GPGPU?
It’s not big enough until it looks like a futuristic airliner engine : )
I’m not an expert but from what I gather memory management limitations are the biggest problem with converting algorithms to run on a GPGPU. And if its not a parallizable task there is no benefit in doing so, since each individual core on a GPU is slower than the main CPU cores.
Anyway the prediction is that eventually we won’t have seperate CPU / GPU we will just have CPU’s with hundreds of cores on a single die, which at that point will be more efficient at graphics tasks than a GPU. For power saving you’ll also be able to turn on and off individual cores or run some of them at different speeds that others.