This is a really technical topic, and probably belongs on a different forum (if you know a good one, let me know!)
I just bought an Altera DE2 fpga* board which has two connectors to the outside world, a pair of 40-pin headers that are identical to a IDE. I’d like to build an expansion module that plugs into those headers and connects the signals to a couple of PCI slots. I’ve studied the issue extensively, and the fpga seems to fully support PCI signaling (clamp diodes, etc.) and the two headers have enough pins for the signals. (Well… I’m pretty sure of these things, anyway.)
I’ve also figured out how to do this: I studied the PCI spec, ordered the connectors from digikey, and will order a pcb to be manufactured at either pcbexpress.com or expresspcb.com (yeah… great branding or what!). I’ve downloaded KiCad and a few others to do the CAD and have started to use them.
The only thing left is to do the actual PCB layout. It has to, of course, work and it’d be nice for it to have good signal quality afterward (hopefully, enough for PCI 32bit/66MHz operation). I’ve never ever done this before, though, and although I can connect one pin to another as good as anyone else, there’s signal quality issues like cross-talk, capacitative coupling, etc. that I only somewhat understand.
Any tips/resources?
*An FPGA is a microchip that can morph into any other microchip. Yeah, it’s freakin cool.
If you keep all the traces as short as practical, and try to keep them all close to the same length, you should be fine. 66MHz is not very high speed. I designed and routed a PCI card using a PLX part, and it worked fine, even though I didn’t use any sophisticated signal-integrity tools to verify it.
Also be sure to include a large ground plane–big areas of copper which serve as a ground bus. A large ground plane reduces RFI both in and out and results in fewer headaches at high frequencies. Also, since you’re using an Altera product, I assume you’ll be using their Quartus II software? If you find yourself bogged down in it, feel free to contact me and I can give you some guidance and/or put you in touch with one of the EEs at work; some of our high-end product line uses Altera FPGA cores.
This is something I worry about. How close is close? The traces are already a bit asymmetric when they get to the headers, and after that… This brings me to a big question: how narrow can I make the traces? I’d like to use a 2-layer board, and if, at times, the traces go down to about 7-8 mils, I could squeeze them in between the pads and everything would be nice and straight and clean. Will that hurt signal quality / impedence? And how big should i make the solder pads?
On a different topic, the cheap processes on expresspcb.com are 2 layers w/o solder-mask/silkscreen. Will having 7 mil traces w/o soldermask be very fragile?
Not really fragile, as such, but without a solder mask you need to be VERY careful to avoid solder bridges, assuming you’ll be populating the board yourself. And even if you’re not, I’d inspect it very carefully under magnification before using it. We get our boards–some multilayer with fine-pitch quad chips–produced offsite and even with the solder mask, we do occasionally see bridges between those very tightly-spaced leads.
With a 2-layer board and the 2 voltages + ground needed by PCI, it’s a bit harry. I understand that a signal shouldn’t travel over a split power plane, and that I need capacitive decoupling? A webpage for a different diy expansion board says you must use a 10-100uF and a 1uF capacitor in parallel b/w the +V and GND. For 2 voltages, I should have four capacitors total? As for arranging the layers, I’m thinking dedicating one layer to +5V and +3.3V and another for signals + fill ground region?
p.s. re thanks soldermask! I guess that’s why they call it solder-mask. :rolleyes: The price difference is $100 vs $50, but I think I’ll go with the soldermasked service because my soldering equipment and skills are very rudimentary.
Sounds like good, conservative design to me. Keep those decoupling caps as close to the individual chip leads as possible. As for soldering, if you’re doing any significant amount of SMD work, get yourself a hot air station and some solder paste. You’ll thank me later.
Without looking at your timing and skew budget, I can’t give you an exact figure, but I consider “close” to be within an inch for this sort of design. As far as lines and spaces, I consider anything smaller that 7mil lines with 8mil spaces to be “tight.” I’ve made boards with 6/6 in production, but it starts to get expensive (you get lots of failures when electrically testing the bare boards). I usually try to keep the majority of the board above 10/10, and only reduce the spacing where I absolutely have to. Note that A 4-layer board (dedicated power and ground planes) will make routing much, much easier, and will improve your signal integrity a lot…
I couldn’t open up your link, but I found this: http://www-master.ufr-info-p6.jussieu.fr/2005/IMG/pdf/03c_pci_overview.pdf
Looks like PCI can tolerate 2nS of skew. That’s around 16" of trace length. Keeping the length difference under 2" should be fine. Note however, the restriction in my link that states that the entire trace length on a PCI expansion card must be <2". How does this impact your design?
Hi, Alex, and welcome to the wonderful world of FPGAs! I’m a Xilinx user myself, and am not as intimately familiar with the Altera Cyclone FPGAs as I am with the roughly-equivalent Xilinx Spartan3 series that I use. Still, most of the basics of FPGA design apply equally to “Brand A” and “Brand X” devices.
From your OP, it sounds as though this may be one of your first FPGA projects. Is that the case? If so, be aware that it’s not going to be trivial getting a PCI host up and running, although it should certainly be possible. I hope that you’ve set aside plenty of time for testing! (From your description, it’s a host that you’re building not a peripheral, right?)
Have you checked out comp.arch.fpga ? It’s been around for ages – the Usenet archive goes back to 1994 – and has some highly knowledgeable and helpful active posters.
AFAIK, the I/O pins on your Cyclone II EP2C35 FPGA are PCI-compliant. A quick glance at the DE-2 boards User Manual(warning: 3MB PDF) shows the Expansion Header pinout on page 35. You have 72 I/O lines available, which should easily be enough for 32-bit PCI. It’s worth noting, however, that there is a 47 Ohm resistor in series with each I/O (to limit FPGA I/O current, in concert with the back-to-back diodes for overvoltage protection) – I’m a little concerned that the increased series impedance might throw you out of PCI compliance, at least at 66MHz. You’d need to be careful to keep trace inductance and capacitance low in any PCI design, but these series resistors will make your work a little harder IMHO. You might want to do some worst-case-scenario calculations to check up on this.
Do you already have a PCI host IP core for your device?
I think that beowulff’s “within an inch” reference was to different trace lengths causing skew between signals, not as a limit on absolute trace length! PCI can certainly handle a few inches of trace (think of the average PC motherboard, or an extender card such as this. Your DE-2 board’s 40-pin connectors have a skew between them, but you can correct for that on the PCB that you’re designing.
If I’ve understood your project and the PCB that you’re designing is purely a passive one (i.e. connectors, traces and bypass capacitors only), it isn’t quite so critical to use a 4-layer PCB as it would be if you had active devices on it. Don’t make the traces too narrow or too close together, however, because high inter-trace capacitance will kill the timing, given the 47 Ohm series resistors.
Finally, have you done a power budget for your PCI connectors? I.e., if you’re planning on powering PCI peripheral cards from the DE-2’s expansion headers, do you have enough current availability on the +5V and (especially) +3.3V lines? If not, you may want to consider powering the PCI peripherals separately by putting 3.3V (and +5V if needed) regulators on the PCB that you’re designing, and powering them with a wall-wart. A side advantage of this method would be that you wouldn’t need to route the +3.3V and +5V traces from the DE-2’s headers, which would ease your signal routing and decoupling problems since the power traces would need to be wide and so take up lots of space. You’d still need a very good ground connection (preferably an entire plane), of course.
[Following on from above post, but missed the Edit Window]
I haven’t had a chance to check out the link in beowulff’s latest post, but it sounds as though the 2" trace length limitation is between the edge connector and controller on a peripheral card, which is a bit different from a host backplane such as the one that I think the OP is building. Trace impedance and delays get quite complicated with PCI and its use of signal reflection – 66MHz may not sound particularly fast these days, but it’s still a bit of a “black art” for 32-bit buses at that clock speed.
I’m using Altera’s SoPC software. This is a magical java GUI application that lets you insert and configure various IP and connect them together with Avalon buses. You click a few buttons, connect some lines, and hit Generate. There’s IP for a microcontroller (the NIOS II, which comes with a wonderful IDE), memories, the PCI bus, and a kitchen sink. All that’s left is pin assignment (and microcontroller programming, which is something more familiar to me).
I should’ve just c&p the #s here. 2 ns is i think the max clock skew between components, which is like the maximum distance between two pci slots. 16 inches sounds like quite a distance. The PCI docs say that for 66MHz the “maximum propagation time” and the “CLK to Signal Valid Delay”, whatever those might be exactly, are 6ns. I’m guessing I’ll be fine.
Now we’re getting to the heart of the matter. How can I stop capacitance? I started doing a bit of layout in KiCad. If putting 98% of the signals on one layer, 7 mil traces + 8 mil spaces are perfect for snaking the pci traces between the pin holes. In some sections I can go as high as 12 + 13, but that’s the max. Is this too tight? If I do routing on two layers, it would improve the situation. However, if I go 4-layer then it certainly won’t be soldermasked so even with 4 layers i’d prefer to keep most of the routing on one side.
Re: power. I’ll be putting one sata controller and one gigabit controller on the bus, and those should only use a few watts each. The issue is the +12V and -12V. Do typical cards use them?
Alex -
Check these guys out: http://www.protoexpress.com/
You can get a fully-functional (soldermask, silkscreen, etc.) 4-layer board very reasonably. User their “no-touch” system, which means the board must pass their automated DRC. If it doesn’t, they won’t touch it.
The more I think about it, the more convinced I am that you should externally power your PCI backplane PCB. Even at a “few Watts” for each PCI card, you’re still looking at probably >1 Amp from the +3.3V line, and I’d be willing to bet that your DE-2 board doesn’t have that much spare current capacity for the header connectors – I’m a little surprised that there isn’t an I[sub]3.3V/sub value quoted in the DE-2 manual. It might be worth e-mailing Altera to see if they’ll give you a figure. Still, remember that the 3.3V regulator (probably linear not switching, although the manual doesn’t have a schematic) on the DE-2 already has to power the FPGA and all other on-board 3.3V circuitry; I would think that there’s a major danger of overheating if you try and make it work for much of an off-board load as well.
Although you could use a wall-wart and put a +3.3V regulator (also +5V, +12V, and -12V as necessary), the simplest thing might be to get hold of an old PC ATX power supply and put a 24-pin ATX PS connector on your new PCB. That saves you a lot of time and guarantees all voltages, but takes up more space than a wall-wart / regulator setup. You’d need to provide a “power good” signal back to the PSU, and perhaps guarantee a minimum load with a power resistor (in case you’re testing with no PCI boards in the backplane), but it’s still easier than laying out and mounting multiple voltage regulators.
You might want to check whether or not your target PCI boards require 5V, +12V, and -12V. If the specs don’t tell you, look at the edge connector: if the relevant “gold finger” trace is hooked up to anything on the board, you’re going to need that voltage!
As I said above, powering externally means that you don’t need to run the +3.3V and +5V traces from the DE-2. It also reduces the chance that a short will smoke your expensive FPGA board! (It’s worth it just for that…) Shorting an I/O line to ground won’t hurt the FPGA even if it’s configured as an output (especially with the 47 Ohm series resistors).
So, I’d suggest laying your “backplane” PCB out as:
Header JP2 -- Header JP1 -- PCI slot A -- PCI slot B -- power connector
(all connectors parallel to each other, vertical to this page), so that the new PCB is parallel to, but with vertical and horizontal offsets from, the DE-2 board. The 40-pin female headers will mount on the bottom side to mate with the DE-2, and the PCI and ATX sockets on the top side (you are using straight-through pin 40-pin female headers, NOT ribbon cable, right?)
You should now have space to run all traces on a 2-layer board: signals on one side, ground plane on the other. You also have space for the power traces coming to the PCI connectors from the right-hand side of the PCB (in my diagram above). If you don’t have space to run the power traces between PCI slot A and PCI slot B (the area of maximum congestion), just carefully point-to-point solder wires (make sure they can carry at least 1 Amp, and don’t let them short against anything else!!) between the “power pins” of the two PCI connectors. This will save you the expense of a 4-layer board. You also don’t need a silkscreen for such a simple project – but a solder mask is always worth it for high-density PCBs.
Don’t forget that you still need decoupling capacitors even if the PCI board isn’t powered from the DE-2!
Don’t forget that PCI uses reflected-wave switching, so for most parts of the bus path, the transmitted signal travels out and back before being latched into a receiver. This means that effective trace distances often turn out twice the physical length due to the reflection. Be conservative in your error estimates – trace length differentials count double what you’d think!
However, in your case, load capacitance is probably going to have a more significant effect on timing than trace length, because of those 47 Ohm series resistors. If the total load on the I/O line is 50pF (typical, IMHO), that’s a time constant for signal rise or fall of around 2.5ns right there.
I would seriously recommend planning on getting things running with a 33MHz PCI clock before trying 66MHz, just to help with testing.
Do you have a good fast digital storage oscilloscope handy for verifying the PCI bus timing?
Keep signal traces as far apart as possible, and where they have to run close (i.e. between PCI connectors A and B), keep that part as short as possible! Power traces (+3.3V especially) should be as wide as possible (at least 30 mils and preferably 50 mils if you can), or use point-to-point wiring as per my previous post.
Quick final though: although the DE-2 board has a committed ground plane, and your PCI backplane PCB should have a near-ground plane even with 2 layers, there’ll be a break in planes through the 40-pin headers. Since you’ll end up with more I/O lines (72) through the headers than you need for 32-bit PCI, you might want to consider strapping some of the unused I/O lines to ground on both PCBs, and leaving the respective FPGA pins unassigned. This won’t hurt the FPGA, but may improve your signal integrity. If you do this, try to distribute the new grounds evenly among the I/O lines. Remember, you’re doing single-ended (not differential) switching, and there are currently only 4 ground pins connecting the two boards. Adding more should reduce “ground bounce” when multiple outputs switch simultaneously.
Sorry about the typo. I mean, of course, that you need to provide the “Power On” signal (pin 16 on the 24-pin ATX connector). This is a +3.3V or +5V signal that a motherboard sends to the ATX PSU to turn the latter “On”. This is is usually, of course, in response to a computer’s front panel pushbutton, keyboard “On” button, or Wake-on-LAN signal.
The OP could provide “Power On” from the +3.3V or +5V line of the DE-2 expansion header (there’s very little current draw), via a switch if desired.
Ok, let me share some experience I’ve had so far in one aspect, finding PCB design software. I’ve tried five programs, in order: Altium Designer, KiCad, ExpressPCB, PCB123, and Sprint Layout. Online I found directories that listed many others, but all those programs seemed to be living dinosaurs from decades ago. One even opened a window that a was fn replica of MacOS 7 (its window is a MacOS desktop with a MacOS menu bar on top with its own app windows floating inside)! That’s the gui the program natively ran on, and it all got somehow “ported” to windows. When the installer opened, it looked like Win 3.1. (But I gotta say… holy shit, that app was fast.)
[ul]
[li]Altium looks (from its online demo videos) cool, GUI-oriented, advanced, made by people who “get it.” But I couldn’t use it. Unintuitive garbage.[/li][li]KiCad (GPL) is usually very intuitive and sometimes completely baffling. It had some good features that I was able to figure out, but KiCad’s miss-steps are just jarring. E.g. no undo. Wtf?[/li][li]ExpressPCB, freeware from expresspcb.com, is simple, easy to use, and does right many things KiCad does wrong. It’s got wonderful help files that clearly and concisely explain a lot about pcb design in general. But it’s missing some KiCad stuff I now feel I need, like display of pin numbers. (A PCI connector has 124 pins. No way I’m routing those blind!) The docs themselves, though, are more than worth the download.[/li][li]PCB123, freeware from pcbexpress.com (ahh… those guys are like tweedle-dee and tweedle-dum), is pretty good, maybe the 2nd best. It has an excellent interface (similar to modern CAD programs), and it supports most of the tricks I learned in KiCad last night. There wasn’t any of KiCad’s crazyness. I did get stuck at how to connect througholes to the ground plane. Anyway, the worst part is you can’t really save the files. The program locks you in with the pcbexpress.com website (not too horrible for a small project like this, but still).[/li][li]Sprint-Layout. Finally. A pcb program that doesn’t suck. It’s in some ways similar to pcb123, a little simpler, a bunch more polished. It gets rave reviews on message boards. It’s got one big bug. It doesn’t work well with mils (it’s made by metric Germans), somehow succumbing to rounding error in many circumstances. Sigh. Nevertheless, Sprint-Layout is my choice. Damn the Europeans, but they’ve produced a true star among garbage. This program isn’t free, but it’s only 40 Euros. Wow. (The MacOS mutant wanted $500.)[/li][/ul]
In summary, PCB design software sucks monkey balls (and is a decade behind mechanical CAD), but if you look hard enough you can find something that’ll get the job done.
I actually gave the ribbon cable a lot of thought (examining IDE signals to see which would go through individual wires on an 80-conductor and which through the network of grounds). But then I realized I’m an idiot.
Hmm… 2.5ns sounds pretty good, given that my margin is 6. I think 66MHz is going to work, but it’s not a big deal if it doesn’t. It’s ok if it barely works at all, seeing as this is more of a prototype. Nice thing about PCI is you can turn the frequency down indefinately. You can even talk to it in morse code if that’s all my pcb is good for.
But when you say signal traces should be as far apart as possible, do you mean I should keep them pretty thin (say, 8 mils) just to make the spacing bigger (say, 17 mils)?
Re: Power. I realized another thing, if I wanted to connect the +/-12v at all, it’d have to be to the same psu as the other voltages or i may get a short, wouldn’t I? But for the same reason, powering a PCI card with one psu and its host with another might burn the pci bus, no? An ATX provides a true ground from the wall, but wall-adapters (like the one powering the DE2) don’t, and I’ve measured their fake grounds to differ from real ground by dozens of volts.
(It’s worth it just for that…) Shorting an I/O line to ground won’t hurt the FPGA even if it’s configured as an output (especially with the 47 Ohm series resistors).